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Replies inline.=0A= =0A= > Could the commit message mention the NVM shadow write, the sibling-output= =0A= > phase restart, and the ~100 ms cost per call?=0A= =0A= Yes -- the v9 changelog describes all three. The PLL-wide=0A= divider restart is the chip's only phase-apply mechanism; a per-output flus= h=0A= does not exist in this hardware.=0A= =0A= > Should this bail out apply to every request? [zero cached freq rejects= =0A= > everything]=0A= =0A= Fixed in v9: when the cache is empty the setter seeds the rate from=0A= the divider chain (the same readback frequency_get uses), so boards whose D= T=0A= lists no output frequencies can still adjust phase; the request is only=0A= rejected when the rate cannot be determined at all.=0A= =0A= > Should the positive branch also reduce modulo the output period?=0A= =0A= Yes -- fixed in v9: both branches reduce modulo the output period, so=0A= a positive request larger than one period no longer programs millions of VC= O=0A= cycles of reset delay.=0A= =0A= > nothing recomputes it when the frequency changes later.=0A= =0A= Fixed in v9: a frequency change re-encodes the cached phase adjust=0A= against the new period, so the programmed delay and the reported value stay= =0A= consistent across rate changes.=0A= =0A= > Can a mid-sequence I2C failure commit a half-written delay word?=0A= =0A= v9 saves the five delay bytes before the write=0A= and restores them on a mid-sequence failure before the commit, the same sha= pe=0A= as the DIVO write in the frequency path.=0A= =0A= > Does this match the commit message claim that "what the core reads back i= s=0A= > what the registers hold rather than what was asked for"?=0A= =0A= The getter reports the administrative request, which is the=0A= convention the cache implements; the v9 changelog is reworded to say so.=0A= Sub-step quantisation is bounded by the 30 ps fine step and the request is= =0A= preserved exactly in the cache, so the round trip is stable; reporting the= =0A= quantised register value instead would make a set followed by a get disagre= e=0A= with what userspace asked, which the core's equality short-circuit then tur= ns=0A= into an un-clearable state.=0A= =0A= > should struct dpll_pin_properties::phase_gran be populated too?=0A= =0A= Yes -- fixed in v9: phase_gran is populated so=0A= PHASE_ADJUST_MIN/MAX/GRAN are all reported as driver-api/dpll.rst prescribe= s.=0A= It is set to 1 ps rather than the 30 ps fine step deliberately: requests ar= e=0A= accepted at picosecond resolution and encoded to the nearest achievable=0A= coarse+fine delay, so the request granularity, not the hardware step, is wh= at=0A= the attribute must gate.=0A= =0A= > Could both comments be reworded in terms of the slot [...]?=0A= =0A= Fixed in v9 -- both blocks are stated in terms of the physical slot.=0A=