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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-33bfb19f8cesm4740083eec.2.2026.09.15.23.04.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Sep 2026 23:04:26 -0700 (PDT) From: Qiang Yu Date: Tue, 15 Sep 2026 23:04:21 -0700 Subject: [PATCH 1/4] PCI: qcom: Move PHY init and add PHY reset call to align with HPG Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260915-align_pcie_init_sequence_0916-v1-1-0b2195836f30@oss.qualcomm.com> References: <20260915-align_pcie_init_sequence_0916-v1-0-0b2195836f30@oss.qualcomm.com> In-Reply-To: <20260915-align_pcie_init_sequence_0916-v1-0-0b2195836f30@oss.qualcomm.com> To: Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Vinod Koul , Neil Armstrong , Philipp Zabel Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, Qiang Yu X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789538665; l=11264; i=qiang.yu@oss.qualcomm.com; s=20250513; h=from:subject:message-id; bh=wBvSB5WoOED4qErJlwYmr87tVRah/FuLj4HM3VOi0Vw=; b=wcM+CQ29Wxa0qsL2ZxHWjjmycqeaUP7KCCcteTeY659CQX0oEdm77HKH+Ls0itXWUSF8luEdI pIh/eSwUu0BD5uPtDZJgKpxiRmzQU0856rYaAzbqvhDVUyoYmIuXIQ1 X-Developer-Key: i=qiang.yu@oss.qualcomm.com; a=ed25519; pk=Rr94t+fykoieF1ngg/bXxEfr5KoQxeXPtYxM8fBQTAI= X-Proofpoint-Spam-Info: AW1haW4tMjYwOTE2MDA3NiBTYWx0ZWRfX1WVfhgcS89HH 1tjfwuIvnLn9pFP2W+Hoi+toS6BoyoSLun+nFdO/VvHWNs7gLoSYAuOPv4gcofbmOpig6L8YIbM Qfi6P2vJTSg86KoeHZO8uLmSybqzeAg= X-Authority-Analysis: v=2.4 cv=HrTjiETS c=1 sm=1 tr=0 ts=6aaa316c cx=c_pps a=0uOsjrqzRL749jD1oC5vDA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=EUspDBNiAAAA:8 a=ltsZTcXAoX5SLtwclHIA:9 a=QEXdDO2ut3YA:10 a=mQ_c8vxmzFEMiUWkPHU9:22 X-Proofpoint-ORIG-GUID: Xy_H1bp6MErK18tMYOKUvSOM447Y60u7 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTE2MDA3NiBTYWx0ZWRfX9cmQS1f9JCc6 AqcDHhogKEdfI10qysjffHNxr06OXtC0QKgIJ+z0xu0UmziU0Q//p4G+U3BgbhYNyFt9lsoctfm XajEmZaR2d9jy1sYBxqVFGnHAgrfu1+nW3n4qzL8ZrUKC5AeeUTUXvKpFcZ8HlOVWhbhCrZpKoL +2zYNX+YIJoUZnkHjhF/X5mTUXaImQy3bZ0ZQ7VphXNvK1ierj8Qfwf0iQoXhp1gP6HhOFMRhKZ ijhS4n+NtHNZp+N/3lkvhD+p/niqftuoZ9taDkLhObhytJzByG/P3m46mOfWLAMMM1TTLLzWpZ6 EKcrsUlxkQ7/hm0wkV9KYUZ0snJ+Qb1uRjviz4GzB1Z512RgbBHP3JYcspBOs0+BCnYbHn4YnZy sTt0WlbpIVt9cgakIY/fALWeQNz3moZ1JHELL3J9+Gkw0Mmn6YJ/qwnalyoN/u1SIhb1ddGQjlC ndfHstW0T2hGJGwbBYg== X-Proofpoint-GUID: Xy_H1bp6MErK18tMYOKUvSOM447Y60u7 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-15_05,2026-09-15_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 lowpriorityscore=0 impostorscore=0 bulkscore=0 phishscore=0 malwarescore=0 clxscore=1015 priorityscore=1501 spamscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609160076 HPG requires the controller/PHY GDSCs powered up and all controller/PHY clocks enabled first, then the controller's reset and the PHY's reset toggled together as a group, PARF_DEVICE_TYPE set right after, and the rest of the PARF/DBI config left until the PHY is ready. Make use of phy_init() and phy_reset(), and change the call flow to: qcom_pcie_host_init(): phy_init() (PHY GDSCs/regulators/clocks up) qcom_pcie_ops::init: enable controller clocks assert controller reset phy_reset() (toggle the PHY's own reset) deassert controller reset write PARF_DEVICE_TYPE phy_power_on() qcom_pcie_ops::post_init (rest of the PHY/PARF/DBI setup) phy_init() moves into qcom_pcie_host_init() and phy_exit() into qcom_pcie_host_deinit(), right before and right after they call qcom_pcie_ops::init/qcom_pcie_ops::deinit. Apply this to qcom_pcie_init_2_7_0()/_2_9_0()/_2_3_2()/_2_3_3(). qcom_pcie_init_2_3_3() was enabling clocks after the reset deassert; move that ahead of the reset assert to match the same ordering. Also add or move the PARF_DEVICE_TYPE write to right after the reset group in each of those four functions. For most platforms phy_init()/phy_exit()/phy_reset() are no-ops against their phy_ops, so moving the calls around has no effect yet; the PHY's clocks/reset actually start being driven this way once a later PHY driver change implements phy_ops::init/phy_ops::exit/phy_ops::reset. phy-qcom-pcie2.c does implement phy_init()/phy_exit(), but moving the call site into qcom_pcie_host_init()/qcom_pcie_host_deinit() keeps them at the same point relative to that platform's own clock/reset programming, so its init sequence doesn't change either. Signed-off-by: Qiang Yu --- drivers/pci/controller/dwc/pcie-qcom.c | 165 +++++++++++++++++++++++++-------- 1 file changed, 126 insertions(+), 39 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index ee63a6ec99de..c1792f35f9eb 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -508,6 +508,58 @@ static enum dw_pcie_ltssm qcom_pcie_2_1_0_get_ltssm(struct qcom_pcie *pcie) return (enum dw_pcie_ltssm)FIELD_GET(ELBI_SYS_STTS_LTSSM_STATE_MASK, val); } +static void qcom_pcie_phy_exit(struct qcom_pcie *pcie) +{ + struct qcom_pcie_port *port; + + list_for_each_entry(port, &pcie->ports, list) + phy_exit(port->phy); +} + +static int qcom_pcie_phy_init(struct qcom_pcie *pcie) +{ + struct qcom_pcie_port *port, *failed_port = NULL; + struct device *dev = pcie->pci->dev; + int ret; + + list_for_each_entry(port, &pcie->ports, list) { + ret = phy_init(port->phy); + if (ret) { + dev_err(dev, "phy init failed (%d)\n", ret); + failed_port = port; + goto err_exit_phy; + } + } + + return 0; + +err_exit_phy: + list_for_each_entry(port, &pcie->ports, list) { + if (port == failed_port) + break; + phy_exit(port->phy); + } + + return ret; +} + +static int qcom_pcie_phy_reset(struct qcom_pcie *pcie) +{ + struct qcom_pcie_port *port; + struct device *dev = pcie->pci->dev; + int ret; + + list_for_each_entry(port, &pcie->ports, list) { + ret = phy_reset(port->phy); + if (ret) { + dev_err(dev, "phy reset failed (%d)\n", ret); + return ret; + } + } + + return 0; +} + static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; @@ -791,11 +843,23 @@ static int qcom_pcie_init_2_3_2(struct qcom_pcie *pcie) ret = clk_bulk_prepare_enable(res->num_clks, res->clks); if (ret) { dev_err(dev, "cannot prepare/enable clocks\n"); - regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); - return ret; + goto err_disable_regulators; } + ret = qcom_pcie_phy_reset(pcie); + if (ret) + goto err_disable_clocks; + + writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE); + return 0; + +err_disable_clocks: + clk_bulk_disable_unprepare(res->num_clks, res->clks); +err_disable_regulators: + regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); + + return ret; } static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *pcie) @@ -957,18 +1021,28 @@ static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie) struct device *dev = pci->dev; int ret; + ret = clk_bulk_prepare_enable(res->num_clks, res->clks); + if (ret) { + dev_err(dev, "cannot prepare/enable clocks\n"); + return ret; + } + ret = reset_control_bulk_assert(ARRAY_SIZE(res->rst), res->rst); if (ret < 0) { dev_err(dev, "cannot assert resets\n"); - return ret; + goto err_disable_clocks; } usleep_range(2000, 2500); + ret = qcom_pcie_phy_reset(pcie); + if (ret) + goto err_assert_resets; + ret = reset_control_bulk_deassert(ARRAY_SIZE(res->rst), res->rst); if (ret < 0) { dev_err(dev, "cannot deassert resets\n"); - return ret; + goto err_assert_resets; } /* @@ -977,11 +1051,7 @@ static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie) */ usleep_range(2000, 2500); - ret = clk_bulk_prepare_enable(res->num_clks, res->clks); - if (ret) { - dev_err(dev, "cannot prepare/enable clocks\n"); - goto err_assert_resets; - } + writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE); return 0; @@ -991,6 +1061,8 @@ static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie) * the original failure in 'ret'. */ reset_control_bulk_assert(ARRAY_SIZE(res->rst), res->rst); +err_disable_clocks: + clk_bulk_disable_unprepare(res->num_clks, res->clks); return ret; } @@ -1066,7 +1138,6 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; struct dw_pcie *pci = pcie->pci; struct device *dev = pci->dev; - u32 val; int ret; ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies); @@ -1085,6 +1156,10 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) goto err_disable_clocks; } + ret = qcom_pcie_phy_reset(pcie); + if (ret) + goto err_disable_clocks; + usleep_range(1000, 1500); ret = reset_control_deassert(res->rst); @@ -1099,6 +1174,21 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) /* configure PCIe to RC mode */ writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE); + return 0; +err_disable_clocks: + clk_bulk_disable_unprepare(res->num_clks, res->clks); +err_disable_regulators: + regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); + + return ret; +} + +static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie) +{ + const struct qcom_pcie_cfg *pcie_cfg = pcie->cfg; + struct dw_pcie *pci = pcie->pci; + u32 val; + /* Force PHY out of lowest power state */ val = readl(pcie->parf + PARF_PHY_CTRL); val &= ~PHY_TEST_PWR_DOWN; @@ -1126,19 +1216,6 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) val |= EN; writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); - return 0; -err_disable_clocks: - clk_bulk_disable_unprepare(res->num_clks, res->clks); -err_disable_regulators: - regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); - - return ret; -} - -static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie) -{ - const struct qcom_pcie_cfg *pcie_cfg = pcie->cfg; - if (pcie_cfg->override_no_snoop) writel(WR_NO_SNOOP_OVERRIDE_EN | RD_NO_SNOOP_OVERRIDE_EN, pcie->parf + PARF_NO_SNOOP_OVERRIDE); @@ -1298,10 +1375,14 @@ static int qcom_pcie_init_2_9_0(struct qcom_pcie *pcie) struct device *dev = pcie->pci->dev; int ret; + ret = clk_bulk_prepare_enable(res->num_clks, res->clks); + if (ret) + return ret; + ret = reset_control_assert(res->rst); if (ret) { dev_err(dev, "reset assert failed (%d)\n", ret); - return ret; + goto err_disable_clocks; } /* @@ -1310,15 +1391,26 @@ static int qcom_pcie_init_2_9_0(struct qcom_pcie *pcie) */ usleep_range(2000, 2500); + ret = qcom_pcie_phy_reset(pcie); + if (ret) + goto err_disable_clocks; + ret = reset_control_deassert(res->rst); if (ret) { dev_err(dev, "reset deassert failed (%d)\n", ret); - return ret; + goto err_disable_clocks; } usleep_range(2000, 2500); - return clk_bulk_prepare_enable(res->num_clks, res->clks); + writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE); + + return 0; + +err_disable_clocks: + clk_bulk_disable_unprepare(res->num_clks, res->clks); + + return ret; } static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie) @@ -1335,7 +1427,6 @@ static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie) qcom_pcie_configure_dbi_atu_base(pcie); - writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE); writel(BYPASS | MSTR_AXI_CLK_EN | AHB_CLK_EN, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); writel(GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS | @@ -1447,10 +1538,14 @@ static int qcom_pcie_host_init(struct dw_pcie_rp *pp) qcom_pcie_perst_assert(pcie); - ret = pcie->cfg->ops->init(pcie); + ret = qcom_pcie_phy_init(pcie); if (ret) return ret; + ret = pcie->cfg->ops->init(pcie); + if (ret) + goto err_exit_phy; + ret = qcom_pcie_phy_power_on(pcie); if (ret) goto err_deinit; @@ -1503,6 +1598,8 @@ static int qcom_pcie_host_init(struct dw_pcie_rp *pp) qcom_pcie_phy_power_off(pcie); err_deinit: pcie->cfg->ops->deinit(pcie); +err_exit_phy: + qcom_pcie_phy_exit(pcie); return ret; } @@ -1524,6 +1621,7 @@ static void qcom_pcie_host_deinit(struct dw_pcie_rp *pp) qcom_pcie_phy_power_off(pcie); pcie->cfg->ops->deinit(pcie); + qcom_pcie_phy_exit(pcie); } static void qcom_pcie_host_post_init(struct dw_pcie_rp *pp) @@ -2109,10 +2207,6 @@ static int qcom_pcie_parse_port(struct qcom_pcie *pcie, struct device_node *node if (!port) return -ENOMEM; - ret = phy_init(phy); - if (ret) - return ret; - INIT_LIST_HEAD(&port->perst); ret = qcom_pcie_parse_perst(pcie, port, node); @@ -2157,7 +2251,6 @@ static int qcom_pcie_parse_ports(struct qcom_pcie *pcie) list_for_each_entry_safe(port, tmp_port, &pcie->ports, list) { list_for_each_entry_safe(perst, tmp_perst, &port->perst, list) list_del(&perst->list); - phy_exit(port->phy); list_del(&port->list); } @@ -2170,16 +2263,11 @@ static int qcom_pcie_parse_legacy_binding(struct qcom_pcie *pcie) struct qcom_pcie_perst *perst; struct qcom_pcie_port *port; struct phy *phy; - int ret; phy = devm_phy_optional_get(dev, "pciephy"); if (IS_ERR(phy)) return PTR_ERR(phy); - ret = phy_init(phy); - if (ret) - return ret; - port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL); if (!port) return -ENOMEM; @@ -2398,7 +2486,6 @@ static int qcom_pcie_probe(struct platform_device *pdev) list_for_each_entry_safe(port, tmp_port, &pcie->ports, list) { list_for_each_entry_safe(perst, tmp_perst, &port->perst, list) list_del(&perst->list); - phy_exit(port->phy); list_del(&port->list); } err_pm_runtime_put: -- 2.34.1