[PATCH 0/9] drm/tyr: add CSF firmware interface support

[Laura Nao <laura.nao@collabora.com>]

This series follows up to [1], which adds support for firmware loading
and MCU booting to the Tyr driver. The changes included here were
originally introduced in its v4, then dropped to reduce the scope of
the series, and have been adjusted to work with the HRT (Higher-Ranked
Lifetime Types) driver architecture and I/O projections support recently 
introduced.

The series adds support for the Command Stream Frontend (CSF) firmware
interfaces, enabling communication between the Tyr driver and the MCU
through shared memory.

The firmware binary is first validated to contain the shared section
used for this communication. Firmware sections that need CPU access get
a persistent CPU mapping alongside their GPU mapping, kept for the
lifetime of the driver in the case of the shared section. This is the
foundation for resolving firmware-reported MCU virtual addresses into
validated views of the shared section: addresses are represented with a
dedicated McuVa type nd are resolved into bound-checked and
alignment-checked views. Read-only blocks (control, output) use a freely
cloneable view, while writable blocks (input) use a view that takes an
exclusive claim on its byte range, removing the need for locking around
the interface state.

The global (GLB), command stream group (CSG), and command stream (CS)
interfaces are implemented on top of this, providing access to the
firmware control, input, and output blocks and allowing discovery of the
available CSGs and CSs at runtime. The interface is versioned:
GLB_VERSION is read once at probe time to select the layout matching the
firmware's generation.

The global interface is initialized and programmed during probe and its
readiness is notified through the Job IRQ.

A safe wrapper for arch_timer_get_rate() is also added for programming
the GLB timers, and the CONFIG_64BIT restriction on system memory u64
accesses is dropped so the register bitfields used by these interfaces
work on 32-bit too.

This series is based on drm-rust-next and depends on:
- [PATCH v6 0/2] drm/tyr: add Job IRQ handling [2] and its dependencies

[1] https://lore.kernel.org/all/20260728-fw-boot-b4-v10-0-9187aefa3f2f@collabora.com/
[2] https://lore.kernel.org/all/20260728-tyr-irq-v2-v6-0-15c90baed949@collabora.com/

Signed-off-by: Laura Nao <laura.nao@collabora.com>
---
Daniel Almeida (2):
      drm/tyr: add MappedBo, a kernel BO with an always-valid CPU mapping
      drm/tyr: add McuVa and claim-checked MappedBo views

Deborah Brouwer (2):
      drm/tyr: validate presence of CSF shared section
      rust: time: add arch_timer_get_rate wrapper

Laura Nao (5):
      rust: io: drop the CONFIG_64BIT restriction on system memory u64 access
      drm/tyr: drop unused KernelBo::bo() function
      drm/tyr: add CSF firmware interface support
      drm/tyr: program CSF global interface
      drm/tyr: wait for global interface readiness

 drivers/gpu/drm/tyr/driver.rs               |   33 +-
 drivers/gpu/drm/tyr/fw.rs                   |  148 ++-
 drivers/gpu/drm/tyr/fw/interfaces.rs        | 1524 +++++++++++++++++++++++++++
 drivers/gpu/drm/tyr/fw/interfaces/layout.rs |  152 +++
 drivers/gpu/drm/tyr/fw/interfaces/v1.rs     | 1230 +++++++++++++++++++++
 drivers/gpu/drm/tyr/fw/irq.rs               |    1 -
 drivers/gpu/drm/tyr/fw/parser.rs            |   14 +
 drivers/gpu/drm/tyr/gem.rs                  |  334 +++++-
 rust/helpers/time.c                         |    6 +
 rust/kernel/io.rs                           |    4 +-
 rust/kernel/time.rs                         |   30 +
 11 files changed, 3432 insertions(+), 44 deletions(-)
---
base-commit: d1aec98b17f6ee395097b08ccb03c16d725d4ed1
change-id: 20260901-tyr-interfaces-3dd510152348

Best regards,
-- 
Laura Nao <laura.nao@collabora.com>