From: Jonathan Cameron <jonathan.cameron@oss.qualcomm.com>
To: Nicolin Chen <nicolinc@nvidia.com>
Cc: <will@kernel.org>, <robin.murphy@arm.com>, <jgg@nvidia.com>,
<joro@8bytes.org>, <bhelgaas@google.com>, <praan@google.com>,
<kevin.tian@intel.com>, <kees@kernel.org>, <smostafa@google.com>,
<baolu.lu@linux.intel.com>,
Jean-Philippe Brucker <jpb@kernel.org>,
"Eric Auger" <eric.auger@redhat.com>,
<linux-arm-kernel@lists.infradead.org>, <iommu@lists.linux.dev>,
<linux-kernel@vger.kernel.org>, <linux-pci@vger.kernel.org>,
<skaestle@nvidia.com>, <mmarrid@nvidia.com>,
<skolothumtho@nvidia.com>, <bbiber@nvidia.com>,
<harsha.v@oss.qualcomm.com>
Subject: Re: [PATCH v5 03/15] iommu/arm-smmu-v3: Add Q_POS() macro
Date: Tue, 15 Sep 2026 16:19:02 -0700 [thread overview]
Message-ID: <20260915161902.00006cd1@oss.qualcomm.com> (raw)
In-Reply-To: <1db9d32df4a59dcac286e7a82bc2704cdd69b8e0.1789446520.git.nicolinc@nvidia.com>
On Tue, 15 Sep 2026 09:38:15 -0700
Nicolin Chen <nicolinc@nvidia.com> wrote:
> A queue position, the wrap bit combined with the index, is Q_WRP | Q_IDX.
> It is a (max_n_shift + 1)-bit value that wraps at twice the queue capacity.
> queue_inc_cons(), queue_sync_cons_ovf(), and queue_inc_prod_n() currently
> compute such positions by open-coding the two macros at each call site.
>
> Add a Q_POS() macro and switch the open-coded sites to it.
>
> A subsequent change will build a Q_DIFF() on it, to count the entries that
> a queue pointer moved past.
>
> No functional change intended.
>
> Assisted-by: LLM
> Signed-off-by: Nicolin Chen <nicolinc@nvidia.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@oss.qualcomm.com>
next prev parent reply other threads:[~2026-09-15 23:19 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-15 16:38 [PATCH v5 00/15] iommu/arm-smmu-v3: Add PRI support Nicolin Chen
2026-09-15 16:38 ` [PATCH v5 01/15] iommu/arm-smmu-v3: Disable the impl before disabling the SMMU on shutdown Nicolin Chen
2026-09-15 16:38 ` [PATCH v5 02/15] iommu/arm-smmu-v3: Add arm_smmu_attach_release() Nicolin Chen
2026-09-15 16:38 ` [PATCH v5 03/15] iommu/arm-smmu-v3: Add Q_POS() macro Nicolin Chen
2026-09-15 23:19 ` Jonathan Cameron [this message]
2026-09-15 16:38 ` [PATCH v5 04/15] iommu/arm-smmu-v3: Drain in-flight fault events on domain detach Nicolin Chen
2026-09-15 16:38 ` [PATCH v5 05/15] iommu/arm-smmu-v3: Flush in-flight fault work " Nicolin Chen
2026-09-15 16:38 ` [PATCH v5 06/15] iommu/arm-smmu-v3: Allocate IOPF queue without FEAT_SVA Nicolin Chen
2026-09-15 16:38 ` [PATCH v5 07/15] iommu/arm-smmu-v3: Submit CMDQ_OP_PRI_RESP for IOPF event Nicolin Chen
2026-09-15 16:38 ` [PATCH v5 08/15] iommu/arm-smmu-v3: Disable the queue IRQs before disabling the SMMU Nicolin Chen
2026-09-15 23:21 ` Jonathan Cameron
2026-09-15 16:38 ` [PATCH v5 09/15] iommu/arm-smmu-v3: Disable PRI when no IRQ handler is registered Nicolin Chen
2026-09-15 16:38 ` [PATCH v5 10/15] iommu/arm-smmu-v3: Support PRI Page Request in arm_smmu_handle_ppr() Nicolin Chen
2026-09-15 23:22 ` Jonathan Cameron
2026-09-15 16:38 ` [PATCH v5 11/15] iommu/arm-smmu-v3: Discard partial PRI faults on PRIQ overflow Nicolin Chen
2026-09-15 16:38 ` [PATCH v5 12/15] iommu/arm-smmu-v3: Allocate IOPF queue for ARM_SMMU_FEAT_PRI Nicolin Chen
2026-09-15 16:38 ` [PATCH v5 13/15] PCI/ATS: Add PRI stubs Nicolin Chen
2026-09-15 16:38 ` [PATCH v5 14/15] PCI/ATS: Export pci_enable_pri() and pci_reset_pri() Nicolin Chen
2026-09-15 16:38 ` [PATCH v5 15/15] iommu/arm-smmu-v3: Enable PRI for PCI device in arm_smmu_probe_device() Nicolin Chen
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