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Tue, 15 Sep 2026 13:57:17 -0700 From: Zhi Wang To: , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Peter Colberg , Zhi Wang Subject: [PATCH 02/14] rust: pci: add {enable,disable}_sriov(), to control SR-IOV capability Date: Tue, 15 Sep 2026 23:56:46 +0300 Message-ID: <20260915205659.76841-3-zhiw@nvidia.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260915205659.76841-1-zhiw@nvidia.com> References: <20260915205659.76841-1-zhiw@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF000061C4:EE_|DS2PR12MB9591:EE_ X-MS-Office365-Filtering-Correlation-Id: 104f2caa-ab28-4325-1d55-08df136bfe90 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|82310400026|1800799024|36860700016|7416014|376014|10067099003|3023799007|6133799003|18002099003|22082099003|56012099006|11063799006; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: OUaGGUIO4R0k1oaV2IWwB1II8WIDMHzlPZ4nqIQ/+R2lnG1JL7dLevBQVGKoJsht2k2bGi9cmumZhozvXNEv05dHB3/jCmONl7IZMHu09XGPxG+bxtisJv3Q8KX4yFGnFumIP7odKCfExeru1sdmZv2GXqjHJTv0HnEHt5avSYval7HdkqehttFa6zTtkH2zrvsR2H9gftCYnfE7ZwOvCfgrosb/UTGjZi6GE0yZcDisFIY+fyocUPVxU5vfsVg80siiCNfho5v1zwdU38WsWHzsoJqvqlVo3oEg0HO4dOmUONsqg2BGZ6uStzeClH2biXjG+wLkrjh/1cBfLwWjBc3dGNdAuAJGvP2L+zq0tv6mF8r2WVFfaQ+KcmSG8cs33/eUxJ2+yr7Y+XrUn5z6A3rlZdj5LFT0WaeJWY43i+k8516vZacLD5Uo3yOzUKru X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Sep 2026 20:57:46.0775 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 104f2caa-ab28-4325-1d55-08df136bfe90 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF000061C4.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS2PR12MB9591 From: Peter Colberg Add methods to enable and disable the Single Root I/O Virtualization (SR-IOV) capability for a PCI device. The wrapped C methods take care of validating whether the device is a Physical Function (PF), whether SR-IOV is currently disabled (or enabled), and whether the number of requested VFs does not exceed the total number of supported VFs. Set the flag managed_sriov to always disable SR-IOV when a Rust PCI driver is unbound from a PF device. This ensures that when a Virtual Function (VF) is bound to a driver, the corresponding Physical Function (PF) is bound to a driver, too, which is a prerequisite for exposing a safe Rust API that allows a VF driver to obtain the PF device for a VF device and subsequently access the private data of the PF driver. Suggested-by: Danilo Krummrich Signed-off-by: Peter Colberg Signed-off-by: Zhi Wang --- rust/kernel/pci.rs | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/rust/kernel/pci.rs b/rust/kernel/pci.rs index 641f2000eb52..63fd8167e4ac 100644 --- a/rust/kernel/pci.rs +++ b/rust/kernel/pci.rs @@ -93,6 +93,7 @@ unsafe fn register( (*pdrv.get()).probe = Some(Self::probe_callback); (*pdrv.get()).remove = Some(Self::remove_callback); (*pdrv.get()).id_table = T::ID_TABLE.as_ptr(); + (*pdrv.get()).managed_sriov = true; } // SAFETY: `pdrv` is guaranteed to be a valid `DriverType`. @@ -506,6 +507,38 @@ pub fn set_master(&self) { // SAFETY: `self.as_raw` is guaranteed to be a pointer to a valid `struct pci_dev`. unsafe { bindings::pci_set_master(self.as_raw()) }; } + + /// Enable the Single Root I/O Virtualization (SR-IOV) capability for this device, + /// where `nr_virtfn` is number of Virtual Functions (VF) to enable. + #[cfg(CONFIG_PCI_IOV)] + pub fn enable_sriov(&self, nr_virtfn: i32) -> Result { + // SAFETY: + // `self.as_raw` returns a valid pointer to a `struct pci_dev`. + // + // `pci_enable_sriov()` checks that the enable operation is valid: + // - the device is a Physical Function (PF), + // - SR-IOV is currently disabled, and + // - `nr_virtfn` does not exceed the total number of supported VFs. + // + // The Core device context inherits from the Bound device context, + // which guarantees that the PF device is bound to a driver. + to_result(unsafe { bindings::pci_enable_sriov(self.as_raw(), nr_virtfn) }) + } + + /// Disable the Single Root I/O Virtualization (SR-IOV) capability for this device. + #[cfg(CONFIG_PCI_IOV)] + pub fn disable_sriov(&self) { + // SAFETY: + // `self.as_raw` returns a valid pointer to a `struct pci_dev`. + // + // `pci_disable_sriov()` checks that the disable operation is valid: + // - the device is a Physical Function (PF), and + // - SR-IOV is currently enabled. + // + // The Core device context inherits from the Bound device context, + // which guarantees that the PF device is bound to a driver. + unsafe { bindings::pci_disable_sriov(self.as_raw()) }; + } } // SAFETY: `pci::Device` is a transparent wrapper of `struct pci_dev`.