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Tue, 15 Sep 2026 13:57:33 -0700 From: Zhi Wang To: , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Peter Colberg , Zhi Wang Subject: [PATCH 04/14] rust: pci: add bus callback sriov_configure(), to control SR-IOV from sysfs Date: Tue, 15 Sep 2026 23:56:48 +0300 Message-ID: <20260915205659.76841-5-zhiw@nvidia.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260915205659.76841-1-zhiw@nvidia.com> References: <20260915205659.76841-1-zhiw@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000075F1:EE_|CY8PR12MB7433:EE_ X-MS-Office365-Filtering-Correlation-Id: 895487ba-56da-4d04-57df-08df136c0672 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700016|376014|23010399003|7416014|10067099003|56012099006|5023799004|11063799006|6133799003|18002099003|22082099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: svKW+GPyqJrIZQke0CyKvYUQKpXJvMHf/Page8sY9TPTnkL6D4jFxCV7M54ESXS13ABe9V2LgNcP4zk1LmAT4vth2H44/01J8iZgNsFuN2UckFAk6oBSRFiBn90GikH6qc0d8J0IqB3d+aOBIqg3gxfl2bGLkTpr+wySNtfbCD2J/0zIx19ibsPgLMYHk1kwCFGtZWZ6rEkh4m8wLnc7wo9TYgqOLC3VDfJSUBWkpabcDOPJFANKs+o/oqbOQxazAHhs+kkkhz/odyiuc9JV4n02Un6PyybXUiTCXzGSKApPZXZrGUKitC7JjLxZGkVfSNVgikwUKKE6/c3cOj4lASKsKHTqLgYgPsWGd9ZJXB3LZN960sMBbh7AiiknscRGGeFtQ1H5Bmoi10N6bpXGsg6BY67lvKr3LHcv3Bgm0ftCNt8M7e8VfxKHkUCbQnfr X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Sep 2026 20:57:59.4546 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 895487ba-56da-4d04-57df-08df136c0672 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000075F1.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7433 From: Peter Colberg Add an optional bus callback sriov_configure() to pci::Driver trait, using the vtable attribute to query if the driver implements the callback. The callback is invoked when a user-space application writes the number of VFs to the sysfs file `sriov_numvfs` to enable SR-IOV, or zero to disable SR-IOV for a PCI device. Suggested-by: Danilo Krummrich Signed-off-by: Peter Colberg Signed-off-by: Zhi Wang --- rust/kernel/pci.rs | 56 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/rust/kernel/pci.rs b/rust/kernel/pci.rs index 24b682d4d6da..7f50c1c96a4f 100644 --- a/rust/kernel/pci.rs +++ b/rust/kernel/pci.rs @@ -94,6 +94,10 @@ unsafe fn register( (*pdrv.get()).remove = Some(Self::remove_callback); (*pdrv.get()).id_table = T::ID_TABLE.as_ptr(); (*pdrv.get()).managed_sriov = true; + #[cfg(CONFIG_PCI_IOV)] + if T::HAS_SRIOV_CONFIGURE { + (*pdrv.get()).sriov_configure = Some(Self::sriov_configure_callback); + } } // SAFETY: `pdrv` is guaranteed to be a valid `DriverType`. @@ -150,6 +154,20 @@ extern "C" fn remove_callback(pdev: *mut bindings::pci_dev) { T::unbind(pdev, data); } + + #[cfg(CONFIG_PCI_IOV)] + extern "C" fn sriov_configure_callback( + pdev: *mut bindings::pci_dev, + nr_virtfn: c_int, + ) -> c_int { + // SAFETY: The PCI bus only ever calls the sriov_configure callback with a valid pointer to + // a `struct pci_dev`. + // + // INVARIANT: `pdev` is valid for the duration of `sriov_configure_callback()`. + let pdev = unsafe { &*pdev.cast::>>() }; + + from_result(|| T::sriov_configure(pdev, nr_virtfn)) + } } /// Declares a kernel module that exposes a single PCI driver. @@ -336,6 +354,44 @@ fn probe<'bound>( fn unbind<'bound>(dev: &'bound Device>, this: Pin<&Self::Data<'bound>>) { let _ = (dev, this); } + + /// Single Root I/O Virtualization (SR-IOV) configure. + /// + /// Called when a user-space application enables or disables the SR-IOV capability for a + /// [`Device`] by writing the number of Virtual Functions (VF), `nr_virtfn` or zero to the + /// sysfs file `sriov_numvfs` for this device. Implementing this callback is optional. + /// + /// Further, and unlike for a PCI driver written in C, when a PF device with enabled VFs is + /// unbound from its bound [`Driver`], the `sriov_configure()` callback is invoked to disable + /// SR-IOV before the `unbind()` callback. This guarantees that when a VF device is bound to a + /// driver, the underlying PF device is bound to a driver, too. + /// + /// Upon success, this callback must return the number of VFs that were enabled, or zero if + /// SR-IOV was disabled. + /// + /// See [PCI Express I/O Virtualization]. + /// + /// [PCI Express I/O Virtualization]: https://docs.kernel.org/PCI/pci-iov-howto.html + /// + /// # Examples + /// + /// ``` + /// # use kernel::{device::Core, pci, prelude::*}; + /// #[cfg(CONFIG_PCI_IOV)] + /// fn sriov_configure(dev: &pci::Device>, nr_virtfn: i32) -> Result { + /// if nr_virtfn == 0 { + /// dev.disable_sriov(); + /// } else { + /// dev.enable_sriov(nr_virtfn)?; + /// } + /// Ok(nr_virtfn) + /// } + /// ``` + #[cfg(CONFIG_PCI_IOV)] + fn sriov_configure(dev: &Device>, nr_virtfn: i32) -> Result { + let _ = (dev, nr_virtfn); + build_error!(crate::error::VTABLE_DEFAULT_ERROR) + } } /// The PCI device representation.