[PATCH net-next v15 0/4] ptp: ocp: add TAP CPLD support for ADVA TimeCard X1

[Sagi Maimon <maimon.sagi@gmail.com>]

The ADVA TimeCard X1 (PCI device 0x0410) carries a Lattice MachXO3 CPLD
on the TMC I2C bus.  This series adds access to it and an update path
through devlink flash.

The card has two I2C controllers.  Linux registers only the one at
0x00150000, normally routed to the config EEPROMs; the one at 0x00120000
belongs to the on-card MicroBlaze and is routed to the TMC or M.2 bus as
its firmware selects.  A request/grant handshake re-routes the host
controller onto the TMC bus, where the PCA9548 and the CPLD behind its
channel 0 live.  Everything here is built on that handshake.

Patches 1 and 2 are pre-existing probe-error-path bugs that were buried
in the feature commit in v13; they are split out with Fixes: tags.  Patch
1 is also a prerequisite: patch 3 adds a mutex that ptp_ocp_detach()
destroys, so devlink has to be unregistered first.  Patch 3 adds the bus
arbitration and the read-only interfaces, patch 4 the flashing.

v14: https://lore.kernel.org/netdev/20260914071531.11640-1-maimon.sagi@gmail.com/T/#u

Changes since v14 - all from the automated review of v14:

 - The hand-back never waited.  MBLAZE_GRANTED contains the host's own
   request bits, which the release write clears first, so the poll could
   not iterate and the adapter was unlocked while the controller was
   still on the TMC bus.  It now tests the firmware-owned grant field.
   Measured on the card: the register reads 0x00000012 once the segment
   is handed back, ~670 ms after the release write - so the wait is real
   and a "read 0" test would never have exited.  Patch 3.
 - adva_x1_mblaze_release() and adva_x1_bus_release() return the failure
   instead of only logging it, so an operation over a bus that may still
   be mis-routed fails rather than reporting success.  The adapter is
   still unlocked, since holding the root lock would stall every other
   user with no way out.  Patch 3.
 - fw.cpld is reported for every board that has the part, not only once
   its USERCODE has been read.  devlink resolves the component name from
   ->info_get(), so gating it on the cached identity made a part holding
   a bad image - which answers neither read - impossible to reflash.  The
   value is "unknown" until the read succeeds.  Patch 4.
 - The cached identity is dropped right after ERASE completes rather than
   only after every later check passed, so a failure part-way through no
   longer leaves the pre-flash cpld.id and fw.cpld published.  Patch 4.
 - The one-shot ID bookkeeping moved inside adva_x1_cpld_read_id(), under
   cpld_lock, where a flash that resets it cannot have it overwritten by
   the worker afterwards.  Patch 3.
 - A failing USERCODE read no longer discards the device ID that was just
   read, and the value/validity pair is published with
   smp_store_release()/smp_load_acquire() rather than bare WRITE_ONCE().
   Patch 4.
 - The flash now confirms the part actually entered configuration mode
   (status ENAB) after EN_CFG_TP.  An enable frame that does not latch
   leaves an idle part reporting neither BUSY nor FAILED, the erase and
   page writes are ignored and DONE is still set from the old image, so
   every later check passed and the update was reported successful with
   the flash untouched.  Patch 4.
 - adva_x1_cpld_exit_config() gates the flag on the wait it was already
   doing and retries, instead of recording an exit that may not have
   happened; the flash also retries the exit on entry, so a part left
   latched by an earlier failure is recovered.  Patch 4.
 - An upper bound on the image and a fatal-signal check in the page loop:
   both cpld_lock and the i2c root lock are held for the whole image, so
   the duration was caller-chosen and uninterruptible.  Patch 4.
 - cpld_i2c_adap_nr is serialised against the i2c bus notifier, and the
   lookup runs from the worker rather than once from probe: device_add()
   notifies before linking the device to its parent, so with asynchronous
   probing both writers could miss the same adapter.  A number that fails
   the parent check in adva_x1_bus_claim() is now forgotten so the lookup
   runs again.  Patch 3.
 - A mux channel select reported as failed may still have been ACKed, so
   the deselect runs on that path too rather than handing the mux back
   with a channel possibly open; a failed deselect is no longer silently
   dropped.  Patches 3 and 4.
 - The CPLD component reports a terminal "Flash complete"/"Flash error"
   status like the SPI path, and the pre-refresh DONE check logs and sets
   extack like the post-refresh one.  Patch 4.
 - linux/iopoll.h and linux/firmware.h moved to patch 4, where their
   first users are.  Comments no longer describe an upload path that only
   exists in the later patch, and the documentation no longer claims .jed
   containers are rejected - only the page-multiple length is checked.
 - Documentation no longer says the identification read happens once: a
   successful update re-arms it.

Tested on an ADVA TimeCard X1: a full erase/program/refresh cycle of a
6526-page image through "devlink dev flash ... component fw.cpld",
cpld_status reading done afterwards and across a reboot, and the
rejection paths for a .jed image and an unknown component name.


Sagi Maimon (4):
  ptp: ocp: unregister devlink before detach on probe error
  ptp: ocp: fix dpll cleanup on probe error
  ptp: ocp: add TAP CPLD access for ADVA TimeCard X1
  ptp: ocp: add TAP CPLD flashing via devlink

 Documentation/ABI/testing/sysfs-timecard     |  29 +
 Documentation/networking/devlink/index.rst   |   1 +
 Documentation/networking/devlink/ptp_ocp.rst |  75 ++
 MAINTAINERS                                  |   1 +
 drivers/ptp/ptp_ocp.c                        | 939 ++++++++++++++++++-
 5 files changed, 1039 insertions(+), 6 deletions(-)
 create mode 100644 Documentation/networking/devlink/ptp_ocp.rst


base-commit: 87b80c2f6b05cad9f0ff9136709c62a0f59923e3
-- 
2.47.0