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Wed, 16 Sep 2026 11:37:58 -0700 From: To: , , , , , , , , , , , , , , , , , , , , CC: , , , , , , , , , , , Subject: [PATCH v5 13/27] vfio/pci: Bracket PCI resets with the CXL reset hooks Date: Thu, 17 Sep 2026 00:05:26 +0530 Message-ID: <20260916183540.3813685-14-mhonap@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260916183540.3813685-1-mhonap@nvidia.com> References: <20260916183540.3813685-1-mhonap@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail202.nvidia.com (10.129.68.7) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN6PEPF00000075:EE_|SJ0PR12MB7081:EE_ X-MS-Office365-Filtering-Correlation-Id: 445c10df-50a1-4929-e78b-08df1421b514 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|7416014|376014|36860700016|23010399003|18002099003|22082099003|56012099006|10067099003|921020|11063799006; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: IvPBJgrmiXugV89yOAHrRqtOvZqJgjSv82RTsV+i1oIbsDECNIIaNwKz7mhUUJPr8dwRY6eFOdLCzw4kTUY4GvTRIvGqxocrnNstbXkqx6UquOcTfnScY1B5wSVU43YM+zPQ9vkCPDZ+DjTSSZgBAUtPGMKiey2ItVxIijnwCAM+AzZxxkRpDMj/RFe6t/h4SvD3/J1hnIsM5hIenu5GkN1upPswXFlBEsHI1xu+Vnwik8ERvIzaJRKVSiOICrpLY6i62dgTmDIJPfc1vtcSa83Td3XVba1+GUL/xbB5YeTLLSVcj4xyMCQW3z+ZigSkp344BTlZ07sB/iyRVFpVV9g7PVzDmXBK+93xYYQZg5jkQbECDpGkyHxmrW/SNZNQGL2b+YeAVbYRKzeXzKckvOEzu9NWeOfX/5IsBy2CeW1MKPn+XOtqnrcq9v+9z9PK X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Sep 2026 18:38:31.2527 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 445c10df-50a1-4929-e78b-08df1421b514 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN6PEPF00000075.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB7081 From: Manish Honap A CXL Type-2 device must quiesce its coherent link before any reset and restore its HDM decoder state afterward, or a reset can leave the device mastering the bus over decoders that are no longer valid. This has to happen around every reset the PCI core drives for the device, not only the ones VFIO issues directly. Add reset_prepare and reset_done to the CXL ops and register the matching pci_error_handlers callbacks. Assisted-by: LLM Signed-off-by: Manish Honap --- drivers/vfio/pci/vfio_pci_core.c | 18 ++++++++++++++++++ include/linux/vfio_pci_core.h | 2 ++ 2 files changed, 20 insertions(+) diff --git a/drivers/vfio/pci/vfio_pci_core.c b/drivers/vfio/pci/vfio_pci_core.c index 2f593b2721a1..a91e07181847 100644 --- a/drivers/vfio/pci/vfio_pci_core.c +++ b/drivers/vfio/pci/vfio_pci_core.c @@ -2794,8 +2794,26 @@ int vfio_pci_core_sriov_configure(struct vfio_pci_core_device *vdev, } EXPORT_SYMBOL_GPL(vfio_pci_core_sriov_configure); +static void vfio_pci_core_reset_prepare(struct pci_dev *pdev) +{ + struct vfio_pci_core_device *vdev = dev_get_drvdata(&pdev->dev); + + if (vdev->cxl_ops) + vdev->cxl_ops->reset_prepare(vdev); +} + +static void vfio_pci_core_reset_done(struct pci_dev *pdev) +{ + struct vfio_pci_core_device *vdev = dev_get_drvdata(&pdev->dev); + + if (vdev->cxl_ops) + vdev->cxl_ops->reset_done(vdev); +} + const struct pci_error_handlers vfio_pci_core_err_handlers = { .error_detected = vfio_pci_core_aer_err_detected, + .reset_prepare = vfio_pci_core_reset_prepare, + .reset_done = vfio_pci_core_reset_done, }; EXPORT_SYMBOL_GPL(vfio_pci_core_err_handlers); diff --git a/include/linux/vfio_pci_core.h b/include/linux/vfio_pci_core.h index 643f32c2141f..6ebf9a26275e 100644 --- a/include/linux/vfio_pci_core.h +++ b/include/linux/vfio_pci_core.h @@ -72,6 +72,8 @@ struct vfio_cxl_ops { void (*release)(struct vfio_pci_core_device *vdev); int (*open_device)(struct vfio_pci_core_device *vdev); void (*close_device)(struct vfio_pci_core_device *vdev); + void (*reset_prepare)(struct vfio_pci_core_device *vdev); + void (*reset_done)(struct vfio_pci_core_device *vdev); /* Pinned per bound CXL device so vfio-cxl cannot unload under usage */ struct module *owner; }; -- 2.25.1