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Wed, 16 Sep 2026 11:36:25 -0700 From: To: , , , , , , , , , , , , , , , , , , , , CC: , , , , , , , , , , , Subject: [PATCH v5 03/27] cxl: Move component register defines to uapi/cxl/cxl_regs.h Date: Thu, 17 Sep 2026 00:05:16 +0530 Message-ID: <20260916183540.3813685-4-mhonap@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260916183540.3813685-1-mhonap@nvidia.com> References: <20260916183540.3813685-1-mhonap@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail202.nvidia.com (10.129.68.7) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV8PEPF00000065:EE_|DM4PR12MB6232:EE_ X-MS-Office365-Filtering-Correlation-Id: 8ed56e37-4068-4f59-3d34-08df14217f83 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|36860700016|376014|23010399003|1800799024|82310400026|10067099003|11063799006|56012099006|6133799003|3023799007|18002099003|22082099003|921020; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: GX9SHoP+C+J0k8kkQWsOtanEZrY4xk8jMbUL02l6FfRbB96eBM9HWJq8N6vV4CpF0zc7/FbM5H4P+TL/UXs3Q4Ou3YWrSa0e0E1PmWBdU2K1V3qgK8TZwnBIK0fDGh/7K6CGKyszAoKum7wxdVt97l11N2M0uqboZ7X6AOQs1waxfXrdufJj6Xqs4WfwDAV9XNKMkk4zUEnzR0jF54p/eexwxVm6vTWXgEH1OM3nNxseXr9fUitSPnCrf2HV8VwbsfOQNFnf8ewmZG8F1IJQIyJkPFuAJOP5h/bYDB7rv6ujEkVRsF46rXJ3sWnfabVvBbkvsv2gybqXUu8Aok/UXDBfacIjLZyu5llZL79YWnGute1tpxGYRAqnF04dLN1L8+eDFWsDLD1WGI5XXH9BQVpCyA6vj1D+WZgcyBCDWucqtssC7IGUNMicWi2+X2sN X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Sep 2026 18:37:01.4424 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8ed56e37-4068-4f59-3d34-08df14217f83 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: LV8PEPF00000065.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6232 From: Manish Honap The CXL component and HDM decoder register layout is spec-defined and is needed by a userspace consumer that cannot include the private drivers/cxl/cxl.h The vfio-cxl selftest (tools/testing/selftests/vfio/vfio_cxl_type2_test.c) builds against installed uapi headers only. Move those defines to a new uapi header, the way PCI register offsets live in uapi pci_regs.h, and include it from drivers/cxl/cxl.h so existing in-kernel users are unchanged. No functional change; the GENMASK and BIT forms are written as plain values as a uapi header requirement. Assisted-by: LLM Signed-off-by: Manish Honap --- MAINTAINERS | 1 + drivers/cxl/cxl.h | 47 +------------------------------- include/uapi/cxl/cxl_regs.h | 53 +++++++++++++++++++++++++++++++++++++ 3 files changed, 55 insertions(+), 46 deletions(-) create mode 100644 include/uapi/cxl/cxl_regs.h diff --git a/MAINTAINERS b/MAINTAINERS index 3a19da74d00c..2037501cd621 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -6573,6 +6573,7 @@ F: Documentation/driver-api/cxl F: Documentation/userspace-api/fwctl/fwctl-cxl.rst F: drivers/cxl/ F: include/cxl/ +F: include/uapi/cxl/ F: include/uapi/linux/cxl_mem.h F: tools/testing/cxl/ diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 03ce50a6a06e..43c30e08df86 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -13,6 +13,7 @@ #include #include #include +#include extern const struct nvdimm_security_ops *cxl_security_ops; @@ -24,52 +25,6 @@ extern const struct nvdimm_security_ops *cxl_security_ops; * (port-driver, region-driver, nvdimm object-drivers... etc). */ -/* CXL 2.0 8.2.4 CXL Component Register Layout and Definition */ -#define CXL_COMPONENT_REG_BLOCK_SIZE SZ_64K - -/* CXL 2.0 8.2.5 CXL.cache and CXL.mem Registers*/ -#define CXL_CM_OFFSET 0x1000 -#define CXL_CM_CAP_HDR_OFFSET 0x0 -#define CXL_CM_CAP_HDR_ID_MASK GENMASK(15, 0) -#define CM_CAP_HDR_CAP_ID 1 -#define CXL_CM_CAP_HDR_VERSION_MASK GENMASK(19, 16) -#define CM_CAP_HDR_CAP_VERSION 1 -#define CXL_CM_CAP_HDR_CACHE_MEM_VERSION_MASK GENMASK(23, 20) -#define CM_CAP_HDR_CACHE_MEM_VERSION 1 -#define CXL_CM_CAP_HDR_ARRAY_SIZE_MASK GENMASK(31, 24) -#define CXL_CM_CAP_PTR_MASK GENMASK(31, 20) - -#define CXL_CM_CAP_CAP_ID_RAS 0x2 -#define CXL_CM_CAP_CAP_ID_HDM 0x5 -#define CXL_CM_CAP_CAP_HDM_VERSION 1 - -/* HDM decoders CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure */ -#define CXL_HDM_DECODER_CAP_OFFSET 0x0 -#define CXL_HDM_DECODER_COUNT_MASK GENMASK(3, 0) -#define CXL_HDM_DECODER_TARGET_COUNT_MASK GENMASK(7, 4) -#define CXL_HDM_DECODER_INTERLEAVE_11_8 BIT(8) -#define CXL_HDM_DECODER_INTERLEAVE_14_12 BIT(9) -#define CXL_HDM_DECODER_INTERLEAVE_3_6_12_WAY BIT(11) -#define CXL_HDM_DECODER_INTERLEAVE_16_WAY BIT(12) -#define CXL_HDM_DECODER_CTRL_OFFSET 0x4 -#define CXL_HDM_DECODER_ENABLE BIT(1) -#define CXL_HDM_DECODER0_BASE_LOW_OFFSET(i) (0x20 * (i) + 0x10) -#define CXL_HDM_DECODER0_BASE_HIGH_OFFSET(i) (0x20 * (i) + 0x14) -#define CXL_HDM_DECODER0_SIZE_LOW_OFFSET(i) (0x20 * (i) + 0x18) -#define CXL_HDM_DECODER0_SIZE_HIGH_OFFSET(i) (0x20 * (i) + 0x1c) -#define CXL_HDM_DECODER0_CTRL_OFFSET(i) (0x20 * (i) + 0x20) -#define CXL_HDM_DECODER0_CTRL_IG_MASK GENMASK(3, 0) -#define CXL_HDM_DECODER0_CTRL_IW_MASK GENMASK(7, 4) -#define CXL_HDM_DECODER0_CTRL_LOCK BIT(8) -#define CXL_HDM_DECODER0_CTRL_COMMIT BIT(9) -#define CXL_HDM_DECODER0_CTRL_COMMITTED BIT(10) -#define CXL_HDM_DECODER0_CTRL_COMMIT_ERROR BIT(11) -#define CXL_HDM_DECODER0_CTRL_HOSTONLY BIT(12) -#define CXL_HDM_DECODER0_TL_LOW(i) (0x20 * (i) + 0x24) -#define CXL_HDM_DECODER0_TL_HIGH(i) (0x20 * (i) + 0x28) -#define CXL_HDM_DECODER0_SKIP_LOW(i) CXL_HDM_DECODER0_TL_LOW(i) -#define CXL_HDM_DECODER0_SKIP_HIGH(i) CXL_HDM_DECODER0_TL_HIGH(i) - /* HDM decoder control register constants CXL 3.0 8.2.5.19.7 */ #define CXL_DECODER_MIN_GRANULARITY 256 #define CXL_DECODER_MAX_ENCODED_IG 6 diff --git a/include/uapi/cxl/cxl_regs.h b/include/uapi/cxl/cxl_regs.h new file mode 100644 index 000000000000..15a5a1930c75 --- /dev/null +++ b/include/uapi/cxl/cxl_regs.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ +/* Copyright (c) 2026 NVIDIA Corporation & Affiliates */ + +#ifndef _UAPI_CXL_REGS_H_ +#define _UAPI_CXL_REGS_H_ + +/* CXL 2.0 8.2.4 CXL Component Register Layout and Definition */ +#define CXL_COMPONENT_REG_BLOCK_SIZE 0x10000 + +/* CXL 2.0 8.2.5 CXL.cache and CXL.mem Registers */ +#define CXL_CM_OFFSET 0x1000 +#define CXL_CM_CAP_HDR_OFFSET 0x0 +#define CXL_CM_CAP_HDR_ID_MASK 0xffff +#define CM_CAP_HDR_CAP_ID 1 +#define CXL_CM_CAP_HDR_VERSION_MASK 0xf0000 +#define CM_CAP_HDR_CAP_VERSION 1 +#define CXL_CM_CAP_HDR_CACHE_MEM_VERSION_MASK 0xf00000 +#define CM_CAP_HDR_CACHE_MEM_VERSION 1 +#define CXL_CM_CAP_HDR_ARRAY_SIZE_MASK 0xff000000 +#define CXL_CM_CAP_PTR_MASK 0xfff00000 + +#define CXL_CM_CAP_CAP_ID_RAS 0x2 +#define CXL_CM_CAP_CAP_ID_HDM 0x5 +#define CXL_CM_CAP_CAP_HDM_VERSION 1 + +/* HDM decoders CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure */ +#define CXL_HDM_DECODER_CAP_OFFSET 0x0 +#define CXL_HDM_DECODER_COUNT_MASK 0xf +#define CXL_HDM_DECODER_TARGET_COUNT_MASK 0xf0 +#define CXL_HDM_DECODER_INTERLEAVE_11_8 0x100 +#define CXL_HDM_DECODER_INTERLEAVE_14_12 0x200 +#define CXL_HDM_DECODER_INTERLEAVE_3_6_12_WAY 0x800 +#define CXL_HDM_DECODER_INTERLEAVE_16_WAY 0x1000 +#define CXL_HDM_DECODER_CTRL_OFFSET 0x4 +#define CXL_HDM_DECODER_ENABLE 0x2 +#define CXL_HDM_DECODER0_BASE_LOW_OFFSET(i) (0x20 * (i) + 0x10) +#define CXL_HDM_DECODER0_BASE_HIGH_OFFSET(i) (0x20 * (i) + 0x14) +#define CXL_HDM_DECODER0_SIZE_LOW_OFFSET(i) (0x20 * (i) + 0x18) +#define CXL_HDM_DECODER0_SIZE_HIGH_OFFSET(i) (0x20 * (i) + 0x1c) +#define CXL_HDM_DECODER0_CTRL_OFFSET(i) (0x20 * (i) + 0x20) +#define CXL_HDM_DECODER0_CTRL_IG_MASK 0xf +#define CXL_HDM_DECODER0_CTRL_IW_MASK 0xf0 +#define CXL_HDM_DECODER0_CTRL_LOCK 0x100 +#define CXL_HDM_DECODER0_CTRL_COMMIT 0x200 +#define CXL_HDM_DECODER0_CTRL_COMMITTED 0x400 +#define CXL_HDM_DECODER0_CTRL_COMMIT_ERROR 0x800 +#define CXL_HDM_DECODER0_CTRL_HOSTONLY 0x1000 +#define CXL_HDM_DECODER0_TL_LOW(i) (0x20 * (i) + 0x24) +#define CXL_HDM_DECODER0_TL_HIGH(i) (0x20 * (i) + 0x28) +#define CXL_HDM_DECODER0_SKIP_LOW(i) CXL_HDM_DECODER0_TL_LOW(i) +#define CXL_HDM_DECODER0_SKIP_HIGH(i) CXL_HDM_DECODER0_TL_HIGH(i) + +#endif /* _UAPI_CXL_REGS_H_ */ -- 2.25.1