From: Vishnu Reddy <busanna.reddy@oss.qualcomm.com>
To: Bryan O'Donoghue <bod@kernel.org>,
Vikash Garodia <vikash.garodia@oss.qualcomm.com>,
Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>,
Abhinav Kumar <abhinav.kumar@linux.dev>,
Bryan O'Donoghue <bod@kernel.org>,
Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>,
Mauro Carvalho Chehab <mchehab@kernel.org>,
"Joerg Roedel (AMD)" <joro@8bytes.org>,
Will Deacon <will@kernel.org>,
Robin Murphy <robin.murphy@arm.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Stanimir Varbanov <stanimir.k.varbanov@gmail.com>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Abel Vesa <abelvesa@kernel.org>
Cc: Krzysztof Kozlowski <krzk@kernel.org>,
linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org,
iommu@lists.linux.dev, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
Vishnu Reddy <busanna.reddy@oss.qualcomm.com>
Subject: [PATCH v11 5/9] media: iris: Handle CPU_CS_SCIACMDARG3 register write via program bootup registers hook
Date: Thu, 17 Sep 2026 10:30:24 +0530 [thread overview]
Message-ID: <20260917-glymur-v11-5-e0c8bc914742@oss.qualcomm.com> (raw)
In-Reply-To: <20260917-glymur-v11-0-e0c8bc914742@oss.qualcomm.com>
On the Glymur platform, the firmware reads CPU_CS_SCIACMDARG3 during boot
to determine the VM count and increments it by 1. Writing the default 0x1
causes the firmware to treat the VM count as 2. To avoid that write 0x0 to
CPU_CS_SCIACMDARG3 as a Glymur platform specific.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com>
---
drivers/media/platform/qcom/iris/iris_vpu3x.c | 6 ++++++
drivers/media/platform/qcom/iris/iris_vpu_common.c | 4 ++--
drivers/media/platform/qcom/iris/iris_vpu_register_defines.h | 1 +
3 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/platform/qcom/iris/iris_vpu3x.c
index 7b07d33d6119..f3c4ee2c4003 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu3x.c
+++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c
@@ -329,6 +329,11 @@ static int iris_vpu36_set_hwmode(struct iris_core *core)
return ret;
}
+static void iris_vpu36_program_bootup_registers(struct iris_core *core)
+{
+ writel(0x0, core->reg_base + CPU_CS_SCIACMDARG3);
+}
+
const struct vpu_ops iris_vpu3_ops = {
.power_off_hw = iris_vpu3_power_off_hardware,
.power_on_hw = iris_vpu_power_on_hw,
@@ -362,6 +367,7 @@ const struct vpu_ops iris_vpu36_ops = {
.power_on_hw = iris_vpu36_power_on_hw,
.power_off_controller = iris_vpu35_vpu4x_power_off_controller,
.power_on_controller = iris_vpu35_vpu4x_power_on_controller,
+ .program_bootup_registers = iris_vpu36_program_bootup_registers,
.calc_freq = iris_vpu3x_vpu4x_calculate_frequency,
.set_hwmode = iris_vpu36_set_hwmode,
};
diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c
index 06e15ea6b58a..e357887624da 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu_common.c
+++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c
@@ -26,7 +26,6 @@
#define QTBL_ENABLE BIT(0)
#define QTBL_ADDR (CPU_CS_BASE_OFFS + 0x54)
-#define CPU_CS_SCIACMDARG3 (CPU_CS_BASE_OFFS + 0x58)
#define SFR_ADDR (CPU_CS_BASE_OFFS + 0x5C)
#define UC_REGION_ADDR (CPU_CS_BASE_OFFS + 0x64)
#define UC_REGION_SIZE (CPU_CS_BASE_OFFS + 0x68)
@@ -67,6 +66,8 @@ static void iris_vpu_setup_ucregion_memory_map(struct iris_core *core)
writel(value, core->reg_base + SFR_ADDR);
}
+ writel(0x1, core->reg_base + CPU_CS_SCIACMDARG3);
+
if (vpu_ops->program_bootup_registers)
vpu_ops->program_bootup_registers(core);
}
@@ -78,7 +79,6 @@ int iris_vpu_boot_firmware(struct iris_core *core)
iris_vpu_setup_ucregion_memory_map(core);
writel(ctrl_init, core->reg_base + CTRL_INIT);
- writel(0x1, core->reg_base + CPU_CS_SCIACMDARG3);
while (!ctrl_status && count < max_tries) {
ctrl_status = readl(core->reg_base + CTRL_STATUS);
diff --git a/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h b/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h
index c44c85eac3b5..3782454b7d06 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h
+++ b/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h
@@ -29,6 +29,7 @@
#define CPU_CS_A2HSOFTINTCLR (CPU_CS_BASE_OFFS + 0x1C)
#define CLEAR_XTENSA2HOST_INTR BIT(0)
+#define CPU_CS_SCIACMDARG3 (CPU_CS_BASE_OFFS + 0x58)
#define CPU_CS_H2XSOFTINTEN (CPU_CS_BASE_OFFS + 0x148)
#define HOST2XTENSA_INTR_ENABLE BIT(0)
--
2.34.1
next prev parent reply other threads:[~2026-09-17 5:01 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-17 5:00 [PATCH v11 0/9] media: iris: Add support for glymur platform Vishnu Reddy
2026-09-17 5:00 ` [PATCH v11 1/9] dt-bindings: media: qcom,glymur-iris: Add glymur video codec Vishnu Reddy
2026-09-17 5:00 ` [PATCH v11 2/9] media: iris: Enable Secure PAS support with IOMMU managed by Linux Vishnu Reddy
2026-09-17 5:00 ` [PATCH v11 3/9] media: iris: Replace enum-indexed clock and power domain tables with per-block structures Vishnu Reddy
2026-09-17 5:00 ` [PATCH v11 4/9] media: iris: Add power sequence for glymur Vishnu Reddy
2026-09-17 5:00 ` Vishnu Reddy [this message]
2026-09-17 5:00 ` [PATCH v11 6/9] media: iris: Add support to select core for dual core platforms Vishnu Reddy
2026-09-17 5:00 ` [PATCH v11 7/9] media: iris: Add platform data for glymur Vishnu Reddy
2026-09-17 5:00 ` [PATCH v11 8/9] arm64: dts: qcom: glymur: Add iris video node Vishnu Reddy
2026-09-17 5:00 ` [PATCH v11 9/9] arm64: dts: qcom: glymur-crd: Enable iris video codec node Vishnu Reddy
2026-09-17 7:09 ` [PATCH v11 0/9] media: iris: Add support for glymur platform Krzysztof Kozlowski
2026-09-17 7:11 ` Krzysztof Kozlowski
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