From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8D10E55C1C5; Thu, 17 Sep 2026 13:57:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789653436; cv=none; b=fSa7QgoCJM1SvRf9BGfeth6S74/v9mUziQ9M2Bj5H5hn9hR2cWt6eZC5GT3KXw7GL3JTs8kdIO2C2IwA2P6W+my0GcMVpWSbdoIIMnTal24VgbfyGJraxXV5GN4q/4C+DRQRhuyxh8JIEMQZoTvwkQ8hIjatn3DRle0Jc1OgQDU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789653436; c=relaxed/simple; bh=5xE5ElBBUihkYKnwR0UoXKzWT+6rxpjmTNNoQUpWXR0=; h=From:Subject:Date:Message-Id:MIME-Version:Content-Type:To:Cc; b=HLSAOyFVqpFpCVMxyUIF6QIv9ythUGjeg8vUe5Os6TlLyqKeP3YUsCiwaPuehFq1e7DlmBxv6HOwPomSmwQvUVtWM2313ajyk4Tads/N+4SwkF8i2IWONUtYo+Adi55hiIj223HDDzOEvBAxEFZEgr4T7gS/hDpW5SgI6ojKGvE= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=E78WIHCu; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="E78WIHCu" Received: by smtp.kernel.org (Postfix) with ESMTPS id 76249C2BCB3; Thu, 17 Sep 2026 13:57:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1789653435; bh=5xE5ElBBUihkYKnwR0UoXKzWT+6rxpjmTNNoQUpWXR0=; h=From:Subject:Date:To:Cc:Reply-To:From; b=E78WIHCu/ZfOwcCrcY7VVQmT09LX39V7+iKqVyuhsW69vAR08NBpN1Zsji2dFHjZd gOSuly4K3xYs7TVptzMC4MkE1Y/OCXREKzPLMuOUQNDiIPIugrGOuFZJv1FhrThVnD wuo6BCzGRJaT6Li7LGmh98je8il3w/QY2/1S4ENuKoSelzePRWAKWNf7T2LTHtLJVw kZu3/8MHQ8TMeJqs4XwjG9u2xB5KnmOwd5Goj2k3eMoy8GLgEfyLF7iPOD034iPD95 z2xkYtmyK+PFALPLHgnZ6FmP6gqVpMExo8S2rNlQx/bbGK7zle2ebl8hLagDwKbagL eF5SgxLZTPneg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4C4E0C982CF; Thu, 17 Sep 2026 13:57:15 +0000 (UTC) From: Sarath Ganapathiraju via B4 Relay Subject: [PATCH v8 0/2] Add LPASS VA CSR HeartBeat pulse clock support Date: Thu, 17 Sep 2026 19:27:13 +0530 Message-Id: <20260917-master-v8-0-823d2c5d090a@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIALnxq2oC/6tWKk4tykwtVrJSqFYqSi3LLM7MzwNyLHQUlJIzE vPSU3UzU4B8JSMDIzMDS0Nz3dzE4pLUIl2zZCNzc4s0U/NEy0QloOKCotS0zAqwQdGxEH5xaVJ WanIJSLdSbS0Ab7+x0WoAAAA= X-Change-ID: 20260917-master-6c2778f57a9a To: andersson@kernel.org, abelvesa@kernel.org, sboyd@kernel.org, bmasney+clk@redhat.com, jbrunet+clk@baylibre.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, srinivas.kandagatla@oss.qualcomm.com, sarath.ganapathiraju@oss.qualcomm.com Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, prasad.kumpatla@oss.qualcomm.com X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789653433; l=4235; i=sarath.ganapathiraju@oss.qualcomm.com; s=default; h=from:subject:message-id; bh=5xE5ElBBUihkYKnwR0UoXKzWT+6rxpjmTNNoQUpWXR0=; b=778m3bD7tLimJw12lPQMr9cN70j0vngxl/2ER1Uaok7iXCWJsIX4JY7dBMvfCPH6RJqtdsoTe /Y/HnrBmSPGCHKOQ9ySQG8rVF161DaiFWUxtZ7eWeESd3GAnVqghXB1 X-Developer-Key: i=sarath.ganapathiraju@oss.qualcomm.com; a=ed25519; pk=4p2FWGXM+F2sir13Lu5stw5aKX5trUymK/ttESvgxQg= X-Endpoint-Received: by B4 Relay for sarath.ganapathiraju@oss.qualcomm.com/default with auth_id=870 X-Original-From: Sarath Ganapathiraju Reply-To: sarath.ganapathiraju@oss.qualcomm.com The LPASS VA CSR block contains rate generator hardware that produces a HeartBeat Pulse (also known as RateGen Pulse). This pulse synchronizes the start of the DMAs and Codec Interfaces for the audio usecases and can serve as a periodic wakeup source for the DSP. This series adds the DT binding and driver support to model this rate generator as a clock provider. Patch 1 adds the YAML binding for the new qcom,hawi-lpass-va-csr clock provider node under Documentation/devicetree/bindings/clock/. Patch 2 adds the lpass-va-csr driver under drivers/clk/qcom that registers the lpass_heartbeat_pulse clock and enables/disables the rate generator via regmap when the clock consumer requests it. Changes in v8: - Rebase the series on linux-next next-20260916. - Require the LPASS LPR and audio vote clocks to access VA CSR register space safely. - Attach the DT vote clocks to runtime PM and resume the device before programming the rate generator registers. - Program the counter and delay registers once during probe. - Use qcom's simple regmap gate ops for the enable bit (Srinivas). - Drop the unreachable of_device_get_match_data() NULL check (Srinivas). - Drop stale Reviewed-by/Tested-by tags after the binding and driver changes. - Link to v7: https://patch.msgid.link/20260831-heartbeat-v7-next-20260828-v7-0-e3ffeac46a51@oss.qualcomm.com Changes in v7: - Rebase the series on linux-next next-20260828. - Add Prasad's Reviewed-by and Tested-by tags to patch 2. - Link to v6: https://patch.msgid.link/20260821-heartbeat-v6-next-20260821-send-v6-0-62c5df84ce21@oss.qualcomm.com Changes in v6: - Rebase the series on linux-next next-20260821. - Capitalize Hawi in binding text (Bjorn). - Simplify the binding example by removing the soc wrapper and two-cell address/size setup (Bjorn). - Keep the full VA CSR register window in the binding and describe it as the VA CSR register block after Konrad clarified the earlier register-range concern (Bjorn, Konrad). - Link to v5: https://patch.msgid.link/20260806-master-20260805-sync-v5-0-0ff42e9b6431@oss.qualcomm.com Changes in v5: - Add explicit ARM64 Kconfig gating and Qualcomm default-module policy for QCOM_CLK_LPASS_HEARTBEAT_PULSE to align with nearby qcom clock entries. - Link to v4: https://patch.msgid.link/20260805-master-20260805-sync-v4-0-dfbcbf427c2c@oss.qualcomm.com Changes in v4: - Rename the binding filename and schema ID to hawi-specific naming: qcom,lpass-va-csr.yaml -> qcom,hawi-lpass-va-csr.yaml (Krzysztof). - Rename Kconfig symbol QCOM_CLK_LPASS_VA_CSR to QCOM_CLK_LPASS_HEARTBEAT_PULSE (Konrad). - Add devm_pm_runtime_enable() in the lpass-va-csr probe path. - Drop the qcom,lpass-va-macro binding extension patch; it will be resubmitted with the Hawi DTSI changes. - Drop sound/soc/codecs/Kconfig select wiring to keep this series clock-only (Konrad). - Link to v3: https://lore.kernel.org/all/20260723-master-v3-0-3d67b79b0515@oss.qualcomm.com/ Changes in v3: - Move the qcom,lpass-va-csr binding under Documentation/devicetree/bindings/clock/ (Krzysztof). - Move the driver under drivers/clk/qcom/ (Krzysztof). - Improve the schema description and use generic clock-controller node naming (Krzysztof). - Use additionalProperties: false and keep compatibles sorted. Changes in v2: - Split the qcom,lpass-va-csr and qcom,lpass-va-macro bindings into separate patches. Changes in v1: - Initial version Signed-off-by: Sarath Ganapathiraju --- Sarath Ganapathiraju (2): dt-bindings: clock: qcom: Add LPASS VA CSR HeartBeat pulse clock clk: qcom: Add LPASS VA CSR heartbeat pulse clock .../bindings/clock/qcom,hawi-lpass-va-csr.yaml | 62 +++++++++ drivers/clk/qcom/Kconfig | 14 +++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/lpass-va-csr.c | 140 +++++++++++++++++++++ 4 files changed, 217 insertions(+) --- base-commit: 0d9d0dbf2fddcff5859d623e90ca73c4054276e1 change-id: 20260917-master-6c2778f57a9a Best regards, -- Sarath Ganapathiraju