From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 83E3F550DC2; Thu, 17 Sep 2026 13:49:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789652979; cv=none; b=nVZM7Lm/2vvrTyXycd/2kYHiovDpv8nCmSc4yhqMSySxxD015jfyDk5XntNVH0exMgswNH0QDJMHZmp/L64etE85MPm+x2KJTi6ajVzVeS8T0dlV0we1UIqv32psyxxNS3qgbAGZ6pxwLWsxwCpuVRY6+w7+w8jK1KgWlG3T/Js= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789652979; c=relaxed/simple; bh=Vwa4GrOJLj5QOmHKF3cPLVhahqIlD9N15DaKOL6XZow=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=QT+3Odl3w+u/otR9XSgdZ6pN4/BTUC48lVDNqwALiI+t1Zs5vUv5oWutQir6N6PlN8TIU3ReSTUAoxt/Fz1sTXZfu5E4Nz1/ZsPCo/BGe2x15oOP54PeAPv5EPnkHKRDEI9+ed9RsFbsIaSl1TcFVKjAKOTXl7/tnhVUSjDDSQI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=gfIW4wmO; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="gfIW4wmO" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1789652962; bh=Vwa4GrOJLj5QOmHKF3cPLVhahqIlD9N15DaKOL6XZow=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=gfIW4wmONU9quRWLErVqefc050kJuXV+HjWpM794SlGC8upnE2Mi5HHh3XO5s25qI rbDMGb3Sdp3Da8aowS0hL1aG89vmR+OiQYTi+wnM12oCRWM26kdbfjA/4OfybptgL+ tfvUJoh7uvFSAnQmHamczcO/ZLy1hy+DiDlylmtrG7qjHEhBSS4SoNhH0OVgQw7ySe tgWmzhgQIBOGvZireXI6d/euEvtIA5abdrfROSFGy8LUKC2zOAKrd5GWrYsFykoUS0 dU5DtIO7FhrSeFIgetjzoiQd9nJDnXedsbjF2Sl0AytF9IHoZk/SyVONee9hiBh4UR 8PM3mEy/4DzgQ== Received: from jupiter.universe (unknown [100.64.1.62]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519) (No client certificate requested) (Authenticated sender: sre) by bali.collaboradmins.com (Postfix) with ESMTPSA id 205A417E0CFC; Thu, 17 Sep 2026 15:49:22 +0200 (CEST) Received: by jupiter.universe (Postfix, from userid 1000) id 8140E480035; Thu, 17 Sep 2026 15:49:21 +0200 (CEST) From: Sebastian Reichel Date: Thu, 17 Sep 2026 15:49:17 +0200 Subject: [PATCH 5/8] PM / devfreq: rockchip-dfi: use bulk clock APIs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260917-rockchip-dfi-cleanup-v1-5-4f00a97a69a6@collabora.com> References: <20260917-rockchip-dfi-cleanup-v1-0-4f00a97a69a6@collabora.com> In-Reply-To: <20260917-rockchip-dfi-cleanup-v1-0-4f00a97a69a6@collabora.com> To: Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Chanwoo Choi , MyungJoo Ham , Kyungmin Park , Sascha Hauer Cc: Nicolas Frattaroli , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, kernel@collabora.com, Sebastian Reichel X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=4096; i=sebastian.reichel@collabora.com; h=from:subject:message-id; bh=lvpRuYQwgyj92YlzDFeJ2yAKSqPbRarTndix/sTx4H4=; b=owJ4nAFtApL9kA0DAAoB2O7X88g7+poByyZiAGqr7+FnCJy/jwMa05leUmYukEYxoMo7+2UL3 rNxQP4QiU6RKYkCMwQAAQoAHRYhBO9mDQdGP4tyanlUE9ju1/PIO/qaBQJqq+/hAAoJENju1/PI O/qahRYQAIcu0Ng3nsVFJwJZlYpx2G5XCANzt/usufe2TdKNle1X8R6GEtNEj6KUTo7LZV+U5+r 6nhf9OvEZrFgqOMBXHCey0Zk0jbklGACrA7uBR6RAdLbN6GMhvq3J75Sf4Sj8bUNBrGYHTG7i/q kBhv3OYcjV93VHPgRl1DYtaOsV5z7CRdD3nmXxT8tEBlo+OQFOD1NJ8goBtKo30BAScKw1VDabO 30Gz9cCf/PFYAtqUSQAI6kpCeWKPVe8VnNYxtmPbMu0nkVb6asaBw3CY/PnXG8zER52pshlqtdK cMfDxSmhaesilCm4R7WkMJkh7jSuC8NmvTnnXRxQBw1rnInxTvCi79OaLbDpEmC+rtQ0wljUPPi u3FmsOolDxiGwfutV30VBePzCbDm/19zPgRySlh2ChV0UcrDVIBgK1VtG4Olav5zYqFnbI/vxvs kmceHjBYQRE5dZkVD1Of6NJZruzp0WbbOEMMTJXOVa76F/9wxCkkZTAN7gg3Vbr5q6Mpe792JAb HVzXca3qoElo5ZqBI4hKZr1E01TAR6P1FC+EdM+L6Y5D4hV4+8pTzJscO805IOt68h/wkvUKiqc 6M6J1KddzhhW7ykW6yWSfc6Cs2++IrN1h6N3C8tcxJJFzW1KLXJRUnacmkx9VWYec1z/jsQSOp1 sSgUTPASSXQQNJZf76GoqkA== X-Developer-Key: i=sebastian.reichel@collabora.com; a=openpgp; fpr=EF660D07463F8B726A795413D8EED7F3C83BFA9A From: Nicolas Frattaroli Currently, the only clock rockchip-dfi will ever use is on the rk3399, namely pclk_ddr_mon. However, this is mainly because every other SoC's mainline clock tree and bindings are probably lying and not telling us about some clock gate branches that do exist in hardware, but nothing happens ever gate. Get preparations out of the way to fix this by moving to the bulk clock APIs, which will make handling the one-clock-per-channel cases easier to deal with. Signed-off-by: Nicolas Frattaroli Signed-off-by: Sebastian Reichel --- drivers/devfreq/event/rockchip-dfi.c | 39 +++++++++++++++++++++++++++--------- 1 file changed, 30 insertions(+), 9 deletions(-) diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c index dd9edfd6a674..b61ec500eaed 100644 --- a/drivers/devfreq/event/rockchip-dfi.c +++ b/drivers/devfreq/event/rockchip-dfi.c @@ -98,7 +98,7 @@ struct rockchip_dfi { struct device *dev; void __iomem *regs; struct regmap *regmap_pmu; - struct clk *clk; + struct clk_bulk_data *clocks; int usecount; struct mutex mutex; u32 ddr_type; @@ -122,6 +122,8 @@ struct rockchip_dfi_variant { int stride; bool ctrl_single; unsigned int max_channels; + const char * const *clk_names; + unsigned int num_clks; }; static int rockchip_dfi_ddrtype_to_ctrl(struct rockchip_dfi *dfi, u32 *ctrl) @@ -183,9 +185,10 @@ static int rockchip_dfi_enable(struct rockchip_dfi *dfi) if (dfi->usecount > 1) goto out; - ret = clk_prepare_enable(dfi->clk); + ret = clk_bulk_prepare_enable(dfi->variant->num_clks, dfi->clocks); if (ret) { - dev_err(&dfi->edev->dev, "failed to enable dfi clk: %d\n", ret); + dev_err(&dfi->edev->dev, "failed to enable dfi clocks: %pe\n", + ERR_PTR(ret)); goto out; } @@ -245,7 +248,7 @@ static void rockchip_dfi_disable(struct rockchip_dfi *dfi) break; } - clk_disable_unprepare(dfi->clk); + clk_bulk_disable_unprepare(dfi->variant->num_clks, dfi->clocks); out: mutex_unlock(&dfi->mutex); } @@ -721,11 +724,6 @@ static int rk3399_dfi_init(struct rockchip_dfi *dfi) struct regmap *regmap_pmu = dfi->regmap_pmu; u32 val; - dfi->clk = devm_clk_get(dfi->dev, "pclk_ddr_mon"); - if (IS_ERR(dfi->clk)) - return dev_err_probe(dfi->dev, PTR_ERR(dfi->clk), - "Cannot get the clk pclk_ddr_mon\n"); - /* get ddr type */ regmap_read(regmap_pmu, RK3399_PMUGRF_OS_REG2, &val); dfi->ddr_type = FIELD_GET(RK3399_PMUGRF_OS_REG2_DDRTYPE, val); @@ -802,11 +800,17 @@ static int rk3588_dfi_init(struct rockchip_dfi *dfi) return 0; }; +static const char * const rk3399_clk_names[] = { + "pclk_ddr_mon", +}; + static const struct rockchip_dfi_variant rk3399_variant = { .init = rk3399_dfi_init, .stride = 0x14, .ctrl_single = true, .max_channels = 2, + .clk_names = rk3399_clk_names, + .num_clks = ARRAY_SIZE(rk3399_clk_names), }; static const struct rockchip_dfi_variant rk3568_variant = { @@ -837,6 +841,7 @@ static int rockchip_dfi_probe(struct platform_device *pdev) struct rockchip_dfi *dfi; struct devfreq_event_desc *desc; struct device_node *np = pdev->dev.of_node, *node; + unsigned int i; int ret; dfi = devm_kzalloc(dev, sizeof(*dfi), GFP_KERNEL); @@ -868,6 +873,22 @@ static int rockchip_dfi_probe(struct platform_device *pdev) desc->driver_data = dfi; desc->name = np->name; + if (dfi->variant->num_clks) { + /* NB: CCF is fine with us leaving this NULL if num_clks = 0 */ + dfi->clocks = devm_kcalloc(dev, dfi->variant->num_clks, + sizeof(*dfi->clocks), GFP_KERNEL); + if (!dfi->clocks) + return -ENOMEM; + + for (i = 0; i < dfi->variant->num_clks; i++) + dfi->clocks[i].id = dfi->variant->clk_names[i]; + + ret = devm_clk_bulk_get(dev, dfi->variant->num_clks, + dfi->clocks); + if (ret) + return dev_err_probe(dev, ret, "failed to get clocks\n"); + } + ret = dfi->variant->init(dfi); if (ret) return ret; -- 2.53.0