From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1A06D34752F; Thu, 17 Sep 2026 01:59:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.8 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789610400; cv=none; b=RSfqVkyBHij55bxp+OjDY/Es7anEoChUHGaN7B4gsb5be2JJW76Er+ZX2P/EVwEvunuy8rC2W9regwtJstUfaHSGGtNROaqw2NN1rIJ36WUf2NOrpwNWLJgKX2VU+7BOaqJ+ycAHvMdp4rpK/ziwVhhLVg/NWe6BwsvwLwza9y0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789610400; c=relaxed/simple; bh=mEctfqcBFUkGui4dySfPkgCutbVBKHcLJpk7Ef1+fXs=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=QenQTaFfxF78f18Qe8jlsKObduhLalpdUq0Nd8MaUP86ueW5egJ0QnlPFcLS5uYlQdfjUxF4IaohCeXdiAN/KvSwo2FYmaS2Lmx7RVatuMwj1ASqyGECw4tNJhIhC6NBCI0OVZMgv1bRWNGFuvUedbmgtz6sAWAUOtQMUSHkMxw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=dqofgnFT; arc=none smtp.client-ip=192.198.163.8 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="dqofgnFT" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1789610399; x=1821146399; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=mEctfqcBFUkGui4dySfPkgCutbVBKHcLJpk7Ef1+fXs=; b=dqofgnFTMC/tW4nIFA7hEhMFPwIFbmvAtB92YSdkAmgZCGzqN6SjZmL2 8Dy0Ed/WNuJNySSM2gtFnYWa67XHYguKy6oLU9nMUs5VnJdo+DrtnCZAQ 7Ac0bywnTw4NM7hMrTRzc960cIPKqty7bzg1xi3vlP9E8aPWxALAX/vYS BgAGkz6yQEXpdoX1vBlZV9OTawwIzgK82ET0glG0z+TSWOWHEljazWMyP Vqq1ggHissoK1wXCd9w1sYmKzq7a5p72CA8bN5mYT0AwjWyNvm269MgsV nJCQ1XZYk3fzQJZKsWnG6G349X6jwsTDU2tScgfcvdg+eHBYrrmp9IjKV g==; X-CSE-ConnectionGUID: IJGoUXEgTUqQ2eG/Rj7g8w== X-CSE-MsgGUID: I16bZymMSFSyLL1SA3CN0Q== X-IronPort-AV: E=McAfee;i="6800,10657,11905"; a="107498570" X-IronPort-AV: E=Sophos;i="6.27,103,1787036400"; d="scan'208";a="107498570" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Sep 2026 18:59:59 -0700 X-CSE-ConnectionGUID: uvUQcHPbQAuIo/sTUjHsGg== X-CSE-MsgGUID: gL5NHgmiT4WXNpkS8oXiDw== X-ExtLoop1: 1 Received: from spr.sh.intel.com ([10.112.229.196]) by fmviesa003.fm.intel.com with ESMTP; 16 Sep 2026 18:59:55 -0700 From: Dapeng Mi To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Zide Chen , Falcon Thomas , Xudong Hao , Dapeng Mi Subject: [PATCH 06/12] perf/x86/intel: Remove incorrect PantherCove PEBS data-source constraints Date: Thu, 17 Sep 2026 09:52:28 +0800 Message-Id: <20260917015234.981153-7-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260917015234.981153-1-dapeng1.mi@linux.intel.com> References: <20260917015234.981153-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Same issue exists on Panther Cove, PEBS data source is valid only for the events: - MEM_TRANS_RETIRED.LOAD_LATENCY (0x1cd) - MEM_TRANS_RETIRED.STORE_SAMPLE (0x2cd) The perfmon database (https://github.com/intel/perfmon) previously tagged additional memory events such as MEM_INST_RETIRED.STLB_MISS_LOADS with L1_Hit_Indication, implying PEBS data-source support, which is incorrect. The database has since been fixed, but intel_pnc_pebs_event_constraints[] still follows the old definition and marks those events as data-source capable. As a result, get_data_src() may decode data-source information for events that do not provide valid PEBS data-source data and mislead users. Remove those non-data-source memory events from the Pather Cove PEBS constraint table so matching falls back to the regular non-PEBS constraints, which already provide the same counter constraints. Also update pnc_latency_data() to decode LOAD/STORE flags explicitly when setting memory operation direction, for consistency with other *_latency_data() helpers. Fixes: d345b6bb8860 ("perf/x86/intel: Add core PMU support for DMR") Signed-off-by: Dapeng Mi --- arch/x86/events/intel/ds.c | 18 +++++------------- 1 file changed, 5 insertions(+), 13 deletions(-) diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c index a4581f292966..7a67fb675b43 100644 --- a/arch/x86/events/intel/ds.c +++ b/arch/x86/events/intel/ds.c @@ -639,7 +639,11 @@ u64 pnc_latency_data(struct perf_event *event, u64 status) val |= P(BLK, NA); src.val = val; - if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW) + if (event->hw.flags & + (PERF_X86_EVENT_PEBS_LDLAT | PERF_X86_EVENT_PEBS_LD_HSW)) + src.mem_op = P(OP, LOAD); + if (event->hw.flags & + (PERF_X86_EVENT_PEBS_STLAT | PERF_X86_EVENT_PEBS_ST_HSW)) src.mem_op = P(OP, STORE); return src.val; @@ -1525,18 +1529,6 @@ struct event_constraint intel_lnc_pebs_event_constraints[] = { struct event_constraint intel_pnc_pebs_event_constraints[] = { INTEL_HYBRID_LDLAT_CONSTRAINT(0x1cd, 0xfc), INTEL_HYBRID_STLAT_CONSTRAINT(0x2cd, 0x3), - INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_LOADS */ - INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_STORES */ - INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_INST_RETIRED.LOCK_LOADS */ - INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_INST_RETIRED.SPLIT_LOADS */ - INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_INST_RETIRED.SPLIT_STORES */ - INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_INST_RETIRED.ALL_LOADS */ - INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_INST_RETIRED.ALL_STORES */ - - INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD_RANGE(0xd1, 0xd4, 0xf), - - INTEL_FLAGS_EVENT_CONSTRAINT(0xd0, 0xf), - INTEL_FLAGS_EVENT_CONSTRAINT(0xd6, 0xf), /* * Everything else is handled by PMU_FL_PEBS_ALL, because we -- 2.34.1