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Thu, 17 Sep 2026 19:22:38 +0000 (GMT) Received: from tuxmaker.lnxne.boe (unknown [9.87.85.9]) by smtpav06.fra02v.mail.ibm.com (Postfix) with ESMTP; Thu, 17 Sep 2026 19:22:38 +0000 (GMT) From: Heiko Carstens To: Alexander Gordeev , Sven Schnelle , Vasily Gorbik , Christian Borntraeger , Mete Durlu , Peter Zijlstra , Mark Rutland , Juergen Christ , Ilya Leoshkevich Cc: linux-kernel@vger.kernel.org, linux-s390@vger.kernel.org Subject: [PATCH 07/12] s390/percpu: Use __PCPU_BEGIN() and __PCPU_END() for inline assemblies Date: Thu, 17 Sep 2026 21:22:32 +0200 Message-ID: <20260917192237.638324-8-hca@linux.ibm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260917192237.638324-1-hca@linux.ibm.com> References: <20260917192237.638324-1-hca@linux.ibm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-TM-AS-GCONF: 00 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTE3MDI3MiBTYWx0ZWRfX1bbLuoX+RnbN Pjgw34L+QwfQbGki6BLLAqXq18/QBlrhQvnjRujUTxGdQmCvaSYr65fUEivZ5c3vDAMSLCpcgvz fsBkUf18xU6DjO5p+uxBZA3QFpuIYIhmzFcB1eqDUxGHI3My3rapwYkoekl23EZVXIAdY3a7v5+ mSIq5Drd6D1kvA2EV57Z7f5m5TxqQ3hFRbOzvo4JJc51h0UR60sqqLhDjWDMeKijE412Runu4bc h1RTlaT+v6+iB5OR3n+1kSkzecvvqL+QJHqGNvUVjTWH3hPbBgQt6oKFKsgeJvnYVpnlOTRhcS2 FVRJxLMBawpt8TdbA8rcBjPgLelYpx1SLr/xniSSoReH/BBS2rWtIq4Zivr4jS0Rs0K1xmjdlSH +QefJ6KEarsbjJh5aK5lA2kMu5Zu4Cp7s7z5aVZfbLa+uHfcueiUPe1Zd8QSqG9AEouywWOW4gU GNpE4Yi+ZBAZQ54PzEQ== X-Authority-Analysis: v=2.4 cv=E/NYNqdl c=1 sm=1 tr=0 ts=6aac3e03 cx=c_pps a=3Bg1Hr4SwmMryq2xdFQyZA==:117 a=3Bg1Hr4SwmMryq2xdFQyZA==:17 a=VdqzKS8jKosA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=V8glGbnc2Ofi9Qvn3v5h:22 a=VnNF1IyMAAAA:8 a=7qROLAO0VneCJbZu0JoA:9 X-Proofpoint-ORIG-GUID: fnSa-aIYxZQm0fSJXsjITVIlcfzmiC0C X-Proofpoint-Spam-Info: AW1haW4tMjYwOTE3MDI3MiBTYWx0ZWRfX46Vhj4syEfgQ XLyIIPcSCxDoxv6QwC7Vxk/e2hJrfM65ITd9RySZ64Hyrrc14BVXl54luL0sT1Tm4zNmQ/oZEnr aLdDnJpImy8sg52oKPZXgqWHpuM1lSI= X-Proofpoint-GUID: fnSa-aIYxZQm0fSJXsjITVIlcfzmiC0C X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-17_04,2026-09-16_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 lowpriorityscore=0 priorityscore=1501 spamscore=0 adultscore=0 clxscore=1015 bulkscore=0 malwarescore=0 suspectscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609170272 Replace the use of MVIY_PERCPU(), AG_ALT(), and MVIY_ALT() within all percpu inline assemblies with __PCPU_BEGIN() and __PCPU_END(), since the begin and end of each inline assembly is the same. Also use consistent names: e.g. __PCPU_MVIY() and __PCPU_AG() instead of the previous MVIY_PERCPU() and AG_ALT(). Furthermore extract DEFINE_GR_NUM and UNDEF_GR_NUM which are used to convert register strings to register numbers. All of this should make the code more readable. No functional change. Signed-off-by: Heiko Carstens --- arch/s390/include/asm/percpu.h | 83 +++++++++++++++++----------------- 1 file changed, 42 insertions(+), 41 deletions(-) diff --git a/arch/s390/include/asm/percpu.h b/arch/s390/include/asm/percpu.h index 0df47ec2e6c7..78c3aaa138f7 100644 --- a/arch/s390/include/asm/percpu.h +++ b/arch/s390/include/asm/percpu.h @@ -92,42 +92,49 @@ * * Inline assemblies making use of this typically have a code sequence like: * - * MVIY_PERCPU(...) <- start of percpu code section - * AG_ALT(...) <- add percpu offset; must be the second instruction - * atomic_op <- atomic op - * MVIY_ALT(...) <- end of percpu code section + * __PCPU_BEGIN(...) <- start of percpu code section + * atomic_op <- atomic op + * __PCPU_END(...) <- end of percpu code section */ #define LC_ALT_ADDR __stringify(LOWCORE_ALT_ADDRESS) -#define MVIY_PERCPU(disp, reg) \ - ".macro GEN_MVIY disp, reg\n" \ - ".set .Lreg,255\n" \ - ".irp rs,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15\n" \ - " .ifc \\reg,%%r\\rs\n" \ - " .set .Lreg,\\rs\n" \ +#define DEFINE_GR_NUM \ + ".macro _GR_NUM opd, gr\n" \ + ".set \\opd,255\n" \ + ".irp rs,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15\n" \ + " .ifc \\gr,%%r\\rs\n" \ + " \\opd = \\rs\n" \ " .endif\n" \ ".endr\n" \ - ".if .Lreg == 255\n" \ + ".if \\opd == 255\n" \ " .error \"Illegal register number\"\n" \ ".endif\n" \ - "mviy \\disp(%%r0),.Lreg\n" \ - ".endm\n" \ - ALTERNATIVE("GEN_MVIY " disp " , " reg "\n", \ - "GEN_MVIY " disp "+" LC_ALT_ADDR " , " reg "\n", \ - ALT_FEATURE(MFEATURE_LOWCORE)) \ - ".purgem GEN_MVIY\n" + ".endm\n" -#define MVIY_ALT(disp) \ - ALTERNATIVE(" mviy " disp "(%%r0),0\n", \ - " mviy " disp "+" LC_ALT_ADDR "(%%r0),0\n", \ +#define UNDEF_GR_NUM \ + ".purgem _GR_NUM\n" + +#define __PCPU_MVIY(lcreg, imm) \ + ALTERNATIVE(" mviy " lcreg "(%%r0)," imm "\n", \ + " mviy " lcreg "+" LC_ALT_ADDR "(%%r0)," imm "\n", \ ALT_FEATURE(MFEATURE_LOWCORE)) -#define AG_ALT(disp, reg) \ - ALTERNATIVE(" ag " reg ", " disp "(%%r0)\n", \ - " ag " reg ", " disp "+" LC_ALT_ADDR "(%%r0)\n", \ +#define __PCPU_AG(reg, lcoff) \ + ALTERNATIVE(" ag " reg ", " lcoff "(%%r0)\n", \ + " ag " reg ", " lcoff "+" LC_ALT_ADDR "(%%r0)\n", \ ALT_FEATURE(MFEATURE_LOWCORE)) +#define __PCPU_BEGIN(lcreg, lcoff, reg) \ + DEFINE_GR_NUM \ + "_GR_NUM .Lreg, " reg "\n" \ + UNDEF_GR_NUM \ + __PCPU_MVIY(lcreg, ".Lreg") \ + __PCPU_AG(reg, lcoff) + +#define __PCPU_END(lcreg) \ + __PCPU_MVIY(lcreg, "0") + #ifndef MARCH_HAS_Z196_FEATURES #define this_cpu_add_4(pcp, val) arch_this_cpu_to_op_simple(pcp, val, +) @@ -151,10 +158,9 @@ do { \ if (__builtin_constant_p(val__) && \ ((szcast)val__ > -129) && ((szcast)val__ < 128)) { \ asm volatile( \ - MVIY_PERCPU("%[lcreg]","%[ptr__]") \ - AG_ALT("%[lcoff]", "%[ptr__]") \ + __PCPU_BEGIN("%[lcreg]","%[lcoff]","%[ptr__]") \ op2 " 0(%[ptr__]),%[val__]\n" \ - MVIY_ALT("%[lcreg]") \ + __PCPU_END("%[lcreg]") \ : [ptr__] "+&a" (ptr__), "+m" (*ptr__), \ "=m" (((struct lowcore *)0)->percpu_register) \ : [val__] "i" ((szcast)val__), \ @@ -164,10 +170,9 @@ do { \ : "cc"); \ } else { \ asm volatile( \ - MVIY_PERCPU("%[lcreg]", "%[ptr__]") \ - AG_ALT("%[lcoff]", "%[ptr__]") \ + __PCPU_BEGIN("%[lcreg]","%[lcoff]","%[ptr__]") \ op1 " %[old__],%[val__],0(%[ptr__])\n" \ - MVIY_ALT("%[lcreg]") \ + __PCPU_END("%[lcreg]") \ : [old__] "=&d" (old__), \ [ptr__] "+&a" (ptr__), "+m" (*ptr__), \ "=m" (((struct lowcore *)0)->percpu_register) \ @@ -190,10 +195,9 @@ do { \ \ ptr__ = PERCPU_PTR(&(pcp)); \ asm_inline volatile( \ - MVIY_PERCPU("%[lcreg]","%[ptr__]") \ - AG_ALT("%[lcoff]","%[ptr__]") \ + __PCPU_BEGIN("%[lcreg]","%[lcoff]","%[ptr__]") \ op " %[old__],%[val__],0(%[ptr__])\n" \ - MVIY_ALT("%[lcreg]") \ + __PCPU_END("%[lcreg]") \ : [old__] "=&d" (old__), \ [ptr__] "+&a" (ptr__), "+m" (*ptr__), \ "=m" (((struct lowcore *)0)->percpu_register) \ @@ -216,10 +220,9 @@ do { \ \ ptr__ = PERCPU_PTR(&(pcp)); \ asm_inline volatile( \ - MVIY_PERCPU("%[lcreg]","%[ptr__]") \ - AG_ALT("%[lcoff]","%[ptr__]") \ + __PCPU_BEGIN("%[lcreg]","%[lcoff]","%[ptr__]") \ op " %[old__],%[val__],0(%[ptr__])\n" \ - MVIY_ALT("%[lcreg]") \ + __PCPU_END("%[lcreg]") \ : [old__] "=&d" (old__), \ [ptr__] "+&a" (ptr__), "+m" (*ptr__), \ "=m" (((struct lowcore *)0)->percpu_register) \ @@ -245,10 +248,9 @@ do { \ \ ptr__ = PERCPU_PTR(&(pcp)); \ asm_inline volatile( \ - MVIY_PERCPU("%[lcreg]","%[ptr__]") \ - AG_ALT("%[lcoff]","%[ptr__]") \ + __PCPU_BEGIN("%[lcreg]","%[lcoff]","%[ptr__]") \ op " %[res__],0(%[ptr__])\n" \ - MVIY_ALT("%[lcreg]") \ + __PCPU_END("%[lcreg]") \ : [res__] "=&d" (res__), [ptr__] "+&a" (ptr__), \ "=m" (((struct lowcore *)0)->percpu_register) \ : [lcreg] "i" (LC_PERCPU_REGISTER), \ @@ -271,10 +273,9 @@ do { \ \ ptr__ = PERCPU_PTR(&(pcp)); \ asm_inline volatile( \ - MVIY_PERCPU("%[lcreg]","%[ptr__]") \ - AG_ALT("%[lcoff]","%[ptr__]") \ + __PCPU_BEGIN("%[lcreg]","%[lcoff]","%[ptr__]") \ op " %[val__],0(%[ptr__])\n" \ - MVIY_ALT("%[lcreg]") \ + __PCPU_END("%[lcreg]") \ : [ptr__] "+&a" (ptr__), "=m" (*ptr__), \ "=m" (((struct lowcore *)0)->percpu_register) \ : [val__] "d" (val__), \ -- 2.53.0