From: Rob Herring <robh@kernel.org>
To: Christian Marangi <ansuelsmth@gmail.com>
Cc: Vinod Koul <vkoul@kernel.org>,
Neil Armstrong <neil.armstrong@linaro.org>,
Manivannan Sadhasivam <mani@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
linux-arm-kernel@lists.infradead.org,
linux-phy@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 1/2] dt-bindings: phy: airoha: Document support for AN7583 Gen3 PCIe PHY
Date: Thu, 17 Sep 2026 16:51:07 -0500 [thread overview]
Message-ID: <20260917215107.GA3884839-robh@kernel.org> (raw)
In-Reply-To: <20260901125819.20378-2-ansuelsmth@gmail.com>
On Tue, Sep 01, 2026 at 02:58:17PM +0200, Christian Marangi wrote:
> Document support for AN7583 PCIe PHY used to make the Gen3 PCIe port
> work. Add the required register to configure the PCIe PHY and provide an
> example for it.
>
> Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
> ---
> .../phy/airoha,an7583-pcie-gen3-phy.yaml | 65 +++++++++++++++++++
> 1 file changed, 65 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/airoha,an7583-pcie-gen3-phy.yaml
>
> diff --git a/Documentation/devicetree/bindings/phy/airoha,an7583-pcie-gen3-phy.yaml b/Documentation/devicetree/bindings/phy/airoha,an7583-pcie-gen3-phy.yaml
> new file mode 100644
> index 000000000000..a8ec5ac781cc
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/airoha,an7583-pcie-gen3-phy.yaml
> @@ -0,0 +1,65 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/airoha,an7583-pcie-gen3-phy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Airoha AN7583 PCI-Express PHY
> +
> +maintainers:
> + - Christian Marangi <ansuelsmth@gmail.com>
> +
> +description:
> + The PCIe PHY supports physical layer functionality for PCIe Gen2/Gen3 port.
> +
> +properties:
> + compatible:
> + const: airoha,an7583-pcie-gen3-phy
> +
> + reg:
> + items:
> + - description: PCIE G3 analog base address
> + - description: PCIE G3 PMA base address
> + - description: PCIE detection time base address
> + - description: PCIE Rx AEQ base address
> +
> + reg-names:
> + items:
> + - const: g3-ana
> + - const: g3-pma
> + - const: xr-dtime
> + - const: rx-aeq
> +
> + phys:
> + items:
> + - description: phandle to QPHY phy for Gen2 support
A phy for the phy... That's kind of odd. It there some reason the gen3
and gen2 phys aren't both linked to the PCIe host and controlled from
there? Doesn't look like there is any interleaved or cross
initialization needed to handle these in one place.
Rob
next prev parent reply other threads:[~2026-09-17 21:51 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-01 12:58 [PATCH v3 0/2] phy: airoha: add support for AN7583 PCIe PHY driver Christian Marangi
2026-09-01 12:58 ` [PATCH v3 1/2] dt-bindings: phy: airoha: Document support for AN7583 Gen3 PCIe PHY Christian Marangi
2026-09-17 21:51 ` Rob Herring [this message]
2026-09-01 12:58 ` [PATCH v3 2/2] phy: airoha: add support for AN7583 Gen3 PCIe PHY driver Christian Marangi
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