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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: bKXXOcHmAYyCxz5eH+vStaAo/8cegurxBCvHkqDH4iUlAbzw9usVfwg061mRX4NGRxyeQo6zvPWWh8ld5y7l8WjTGtPWQxDi60JaicWapCqnqVMyMWi1KhWL2zeoUt0Tpb4Wi4mBvN+hiuPb6Q6JtgtNDql0G5nxKg7VYQ3ckdzMDP5Woxk/Z8SYBkWHz8r09Nu/033PiHblCGGB1Jn9SRB1mHb+l9UUjozsr5VeuYnIyax4dZqKRCgAeL87zrdTmZJui3S7aC4n4cQhu/pxTr0hkgAIQf6CHvZdey3hl34VjBaAF7SW2qhn8V70oFPft00LGPsLPJY37S6Ua9tHFOdl1VNp154WXKfYHTn2eVXpLouM1NEkWH9hgItk22bzKa4kv58nrIRTqD6W/i574S7VnrxQt4b3KP1RTGHOV9q8n0VFF0aqloYKg8GPHheA X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Sep 2026 06:40:20.0355 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 59da483d-9f84-4e92-2d66-08df154fb57d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002310.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CHXPR12MB999244 On Xilinx Versal NET, the ARM SMMUv3 EVENTQ, PRIQ and GERROR interrupts are routed through a vendor-specific Control and Status Register (CSR) block, where they must be enabled, cleared and acknowledged before being forwarded to the parent GIC. This series adds a small irqchip driver for the CSR block that chains to the standard arm-smmu-v3 driver, so the generic SMMUv3 driver needs no changes. Patch 1 adds the DT binding. Patch 2 adds the irqchip driver. Changes in v2: - Posted as a proper threaded series with a cover letter (v1 patches went out individually). - dt-bindings (Krzysztof): - Dropped the irrelevant arm,smmu-v3 consumer node from the example. - Dropped the unused "smmu_irq_csr" label from the example. - Dropped the redundant "binding" from the patch subject. - irqchip driver (Thomas): - Aligned kernel-doc member descriptions and used "interrupt" instead of "IRQ". - Used guard(raw_spinlock)() in the mask/unmask/ack callbacks and addressed the comments related to lock handling. - Thomas suggested using devm-managed allocation and irqdomain APIs; however, the driver is registered via IRQCHIP_DECLARE() and has no associated struct device, so devm APIs cannot be used. This code is left unchanged. Link to v1: https://lore.kernel.org/all/20260817105233.1557748-1-tushar.nimkar@amd.com/ https://lore.kernel.org/all/20260817105251.1557770-1-tushar.nimkar@amd.com/ Signed-off-by: Tushar Nimkar --- Anirudha Sarangi (2): dt-bindings: interrupt-controller: Add Xilinx Versal NET SMMU CSR irqchip: Add Xilinx Versal NET SMMU CSR interrupt controller driver .../xlnx,versal-net-smmu-csr.yaml | 75 +++++++ MAINTAINERS | 10 + drivers/irqchip/Kconfig | 10 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-xilinx-smmu-csr.c | 216 +++++++++++++++++++++ 5 files changed, 312 insertions(+) --- base-commit: 0d9d0dbf2fddcff5859d623e90ca73c4054276e1 change-id: 20260917-smmu-changes-v2-9cf7435d6969 Best regards, -- Tushar Nimkar