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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: AEmKbmed6YXhLONNN4LXGqjifdCQy3vws8Hsh3f2EkQ2h7X7ww4rB+bXbTDWkOrGBJArgOip+dXS82rli2mUq0iYrvaNiZ0dUCML3Kyhy6mfosfpZbePXo8ySjaPZvcVDCftxfAAV54PQ3wo9mWkhuJCzjeD8LaKkC/+kGb4KUCeA5B2zOuX4tm4L+8fS5FFVe2baKDkOobxdSfcczV5Jepkk31pbMMRZDwaYrIl4KuJ/iVcemQ4xaImWMsHDu2/b0OHS4eafjffSZIBcT6nFecjmwspQBkq9hpRnu3Qa7Yhbj/L1KYPmHQDemlIvlZyP7lTtC44vAgmGOVe9D/zw4EjWNvM4X/BO6ADdaFHCia7hvaKu6h1TMux69xybnm87enMFAOjl6EcsyBibyDrC9OKRvlioYF36B+RKBjKv27mwk++G4DtvnoOwhvKMudJ X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Sep 2026 06:40:18.7851 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 596a6c10-534b-4290-a48b-08df154fb4b4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN7PEPF0000009C.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB8946 From: Anirudha Sarangi Add a device tree binding schema for the Xilinx Versal NET SMMU CSR (Control and Status Register) interrupt controller. The SMMU CSR block acts as a vendor-specific interrupt controller in front of the ARM SMMUv3, providing registers to enable and clear standard SMMU interrupts such as EVENTQ, CMDQ_SYNC, GERROR and PRIQ. Interrupts must be acknowledged in this block before being forwarded to the parent interrupt controller (e.g. GIC). Signed-off-by: Anirudha Sarangi Co-developed-by: Tushar Nimkar Signed-off-by: Tushar Nimkar --- .../xlnx,versal-net-smmu-csr.yaml | 75 ++++++++++++++++++++++ 1 file changed, 75 insertions(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/xlnx,versal-net-smmu-csr.yaml b/Documentation/devicetree/bindings/interrupt-controller/xlnx,versal-net-smmu-csr.yaml new file mode 100644 index 000000000000..38b63e51b732 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/xlnx,versal-net-smmu-csr.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/xlnx,versal-net-smmu-csr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx Versal NET SMMU CSR Interrupt Controller + +maintainers: + - Anirudha Sarangi + - Tushar Nimkar + +description: | + The Versal NET platform includes a Xilinx-specific SMMU CSR (Control and + Status Register) block that acts as an intermediate interrupt controller + for ARM SMMUv3. + + The block provides registers to enable, disable and clear the + standard SMMUv3 interrupt sources (EVENTQ, CMDQ_SYNC, GERROR and PRIQ) + before forwarding them to the parent interrupt controller, + typically a GIC. + + The controller receives one parent interrupt and demultiplexes CSR + status bits into the following child interrupt identifiers + 0 - EVENTQ + 1 - CMDQ_SYNC + 2 - GERROR (GLOBAL) + 3 - PRIQ + +allOf: + - $ref: /schemas/interrupt-controller.yaml# + +properties: + compatible: + const: xlnx,versal-net-smmu-csr + + reg: + maxItems: 1 + + interrupt-controller: true + + "#interrupt-cells": + const: 1 + description: | + Single cell containing the child interrupt identifier + 0 - EVENTQ + 1 - CMDQ_SYNC + 2 - GERROR (GLOBAL) + 3 - PRIQ + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupt-controller + - "#interrupt-cells" + - interrupts + +additionalProperties: false + +examples: + - | + #include + #include + + interrupt-controller@eca10000 { + compatible = "xlnx,versal-net-smmu-csr"; + reg = <0xeca10000 0x1000>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; + }; -- 2.34.1