From: Thierry Reding <thierry.reding@kernel.org>
To: Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Thierry Reding <thierry.reding@kernel.org>,
Jonathan Hunter <jonathanh@nvidia.com>
Cc: devicetree@vger.kernel.org, linux-tegra@vger.kernel.org,
linux-kernel@vger.kernel.org,
Thierry Reding <treding@nvidia.com>
Subject: [PATCH 1/5] arm64: tegra: Add missing *-cells properties for I2C controllers
Date: Fri, 18 Sep 2026 11:06:53 +0200 [thread overview]
Message-ID: <20260918-tegra264-i2c-v1-1-3adac7aae717@nvidia.com> (raw)
In-Reply-To: <20260918-tegra264-i2c-v1-0-3adac7aae717@nvidia.com>
From: Thierry Reding <treding@nvidia.com>
The I2C controllers on Tegra264 are missing the #address-cells and
devices are added below them.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra264.dtsi | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
index b84f93ad227e..a5049e1a0571 100644
--- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
@@ -3311,6 +3311,8 @@ i2c2: i2c@c600000 {
compatible = "nvidia,tegra264-i2c";
reg = <0x0 0x0c600000 0x0 0x10000>;
interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
clock-frequency = <400000>;
clocks = <&bpmp TEGRA264_CLK_AON_I2C>,
<&bpmp TEGRA264_CLK_PLLAON>;
@@ -3326,6 +3328,8 @@ i2c3: i2c@c610000 {
compatible = "nvidia,tegra264-i2c";
reg = <0x0 0x0c610000 0x0 0x10000>;
interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
clock-frequency = <400000>;
clocks = <&bpmp TEGRA264_CLK_AON_I2C>,
<&bpmp TEGRA264_CLK_PLLAON>;
@@ -3623,6 +3627,8 @@ i2c14: i2c@c410000 {
compatible = "nvidia,tegra264-i2c";
reg = <0x00 0x0c410000 0x0 0x10000>;
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
clock-frequency = <400000>;
clocks = <&bpmp TEGRA264_CLK_TOP_I2C>,
<&bpmp TEGRA264_CLK_PLLP_OUT0>;
@@ -3638,6 +3644,8 @@ i2c15: i2c@c420000 {
compatible = "nvidia,tegra264-i2c";
reg = <0x00 0x0c420000 0x0 0x10000>;
interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
clock-frequency = <400000>;
clocks = <&bpmp TEGRA264_CLK_TOP_I2C>,
<&bpmp TEGRA264_CLK_PLLP_OUT0>;
@@ -3653,6 +3661,8 @@ i2c16: i2c@c430000 {
compatible = "nvidia,tegra264-i2c";
reg = <0x00 0x0c430000 0x0 0x10000>;
interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
clock-frequency = <400000>;
clocks = <&bpmp TEGRA264_CLK_TOP_I2C>,
<&bpmp TEGRA264_CLK_PLLP_OUT0>;
@@ -3728,6 +3738,8 @@ i2c0: i2c@c630000 {
compatible = "nvidia,tegra264-i2c";
reg = <0x00 0x0c630000 0x0 0x10000>;
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
clock-frequency = <400000>;
clocks = <&bpmp TEGRA264_CLK_TOP_I2C>,
<&bpmp TEGRA264_CLK_PLLP_OUT0>;
@@ -3743,6 +3755,8 @@ i2c1: i2c@c640000 {
compatible = "nvidia,tegra264-i2c";
reg = <0x00 0x0c640000 0x0 0x10000>;
interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
clock-frequency = <400000>;
clocks = <&bpmp TEGRA264_CLK_TOP_I2C>,
<&bpmp TEGRA264_CLK_PLLP_OUT0>;
@@ -3758,6 +3772,8 @@ i2c4: i2c@c650000 {
compatible = "nvidia,tegra264-i2c";
reg = <0x00 0x0c650000 0x0 0x10000>;
interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
clock-frequency = <400000>;
clocks = <&bpmp TEGRA264_CLK_TOP_I2C>,
<&bpmp TEGRA264_CLK_PLLP_OUT0>;
@@ -3773,6 +3789,8 @@ i2c6: i2c@c670000 {
compatible = "nvidia,tegra264-i2c";
reg = <0x00 0x0c670000 0x0 0x10000>;
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
clock-frequency = <400000>;
clocks = <&bpmp TEGRA264_CLK_TOP_I2C>,
<&bpmp TEGRA264_CLK_PLLP_OUT0>;
@@ -3788,6 +3806,8 @@ i2c7: i2c@c680000 {
compatible = "nvidia,tegra264-i2c";
reg = <0x00 0x0c680000 0x0 0x10000>;
interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
clock-frequency = <400000>;
clocks = <&bpmp TEGRA264_CLK_TOP_I2C>,
<&bpmp TEGRA264_CLK_PLLP_OUT0>;
@@ -3803,6 +3823,8 @@ i2c8: i2c@c690000 {
compatible = "nvidia,tegra264-i2c";
reg = <0x00 0x0c690000 0x0 0x10000>;
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
clock-frequency = <400000>;
clocks = <&bpmp TEGRA264_CLK_TOP_I2C>,
<&bpmp TEGRA264_CLK_PLLP_OUT0>;
@@ -3818,6 +3840,8 @@ i2c9: i2c@c6a0000 {
compatible = "nvidia,tegra264-i2c";
reg = <0x00 0x0c6a0000 0x0 0x10000>;
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
clock-frequency = <400000>;
clocks = <&bpmp TEGRA264_CLK_TOP_I2C>,
<&bpmp TEGRA264_CLK_PLLP_OUT0>;
@@ -3833,6 +3857,8 @@ i2c10: i2c@c6b0000 {
compatible = "nvidia,tegra264-i2c";
reg = <0x00 0x0c6b0000 0x0 0x10000>;
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
clock-frequency = <400000>;
clocks = <&bpmp TEGRA264_CLK_TOP_I2C>,
<&bpmp TEGRA264_CLK_PLLP_OUT0>;
@@ -3848,6 +3874,8 @@ i2c11: i2c@c6c0000 {
compatible = "nvidia,tegra264-i2c";
reg = <0x00 0x0c6c0000 0x0 0x10000>;
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
clock-frequency = <400000>;
clocks = <&bpmp TEGRA264_CLK_TOP_I2C>,
<&bpmp TEGRA264_CLK_PLLP_OUT0>;
@@ -3863,6 +3891,8 @@ i2c12: i2c@c6d0000 {
compatible = "nvidia,tegra264-i2c";
reg = <0x00 0x0c6d0000 0x0 0x10000>;
interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
clock-frequency = <400000>;
clocks = <&bpmp TEGRA264_CLK_TOP_I2C>,
<&bpmp TEGRA264_CLK_PLLP_OUT0>;
--
2.55.0
next prev parent reply other threads:[~2026-09-18 9:07 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-18 9:06 [PATCH 0/5] arm64: tegra: Miscellaneous I2C changes on Tegra264 Thierry Reding
2026-09-18 9:06 ` Thierry Reding [this message]
2026-09-18 9:06 ` [PATCH 2/5] arm64: tegra: Add I2C aliases for Tegra264 Thierry Reding
2026-09-18 9:06 ` [PATCH 3/5] arm64: tegra: Add NVIDIA Jetson AGX Thor module EEPROM Thierry Reding
2026-09-18 9:06 ` [PATCH 4/5] arm64: tegra: Add NVIDIA Jetson AGX Thor system EEPROM Thierry Reding
2026-09-18 9:06 ` [PATCH 5/5] arm64: tegra: Add thermal senser for Jetson AGX Thor Thierry Reding
2026-09-18 12:56 ` Thierry Reding
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