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Fri, 18 Sep 2026 08:48:43 +0000 (GMT) Received: from tuxmaker.lnxne.boe (unknown [9.87.85.9]) by smtpav01.fra02v.mail.ibm.com (Postfix) with ESMTP; Fri, 18 Sep 2026 08:48:43 +0000 (GMT) From: Heiko Carstens To: Alexander Gordeev , Sven Schnelle , Vasily Gorbik , Christian Borntraeger , Mete Durlu , Peter Zijlstra , Mark Rutland , Juergen Christ , Ilya Leoshkevich Cc: linux-kernel@vger.kernel.org, linux-s390@vger.kernel.org Subject: [PATCH v2 04/12] s390/percpu: Let MVIY_PERCPU() calculate alternative displacement Date: Fri, 18 Sep 2026 10:48:34 +0200 Message-ID: <20260918084842.2333237-5-hca@linux.ibm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260918084842.2333237-1-hca@linux.ibm.com> References: <20260918084842.2333237-1-hca@linux.ibm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-TM-AS-GCONF: 00 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTE4MDExNyBTYWx0ZWRfX0qpMPW6Z3F5m nvhHkIUDzG7P58H2NnWYn6t78udmy5NNb5px5EqkHgWIBlcXcy3El261ukBGmJgvTcasMOd7GCR EqVqZFVxFwo3sy81Hu/SmMdllF+bAp6ii4uZBp7xQ2VTwzAZ90qEUgCYGLrj3AudTkHNm+DKP6L QcD6WKw1rUSLOjz9iCy/Q1s/2nEsWeYK2FKh5hEX70YOpEKX46ef9IVqLwwP2BzdxAj3/lVfOGX 0bSDwZ3SouJLMw0bwlEk8EMyj2EU1M/VZCOipPX9IBSHoJUmVC0iDBjueLZg1hQ/yxrobduZPL6 372uXVV+s+LUPN0hRjwyaYHqlnJ52Ma+BmwzBzUd46+3Mj5qSfMBHABqn5a0uiJNK9vw7uLFCsj JK2zg0y7Eg3ZaxP405LLqdpDWTCup4DIgkrqZEVX/4ykHau50itzYG40k20/SrLEF2dYE1XWQdK AwMxdmwxo1BlcnGaTkg== X-Authority-Analysis: v=2.4 cv=E/NYNqdl c=1 sm=1 tr=0 ts=6aacfaf0 cx=c_pps a=3Bg1Hr4SwmMryq2xdFQyZA==:117 a=3Bg1Hr4SwmMryq2xdFQyZA==:17 a=VdqzKS8jKosA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=V8glGbnc2Ofi9Qvn3v5h:22 a=VnNF1IyMAAAA:8 a=WUj23-fQfn3YcGJ_ZbEA:9 X-Proofpoint-ORIG-GUID: jtZjQXOskH2ppQ1dFX39kXF4IhdF70Us X-Proofpoint-Spam-Info: AW1haW4tMjYwOTE4MDExNyBTYWx0ZWRfXygQhBdXsvlzw 6gCtcujJODwkyqtnvi6bILESs3gteSzfw0YfirzbJib+2sa8e7BU/Dx/NGPQl9PKBvi6EduEKBQ r5uhLS7QJ1eFhvRT3NAyxXGr/1uPqnM= X-Proofpoint-GUID: jtZjQXOskH2ppQ1dFX39kXF4IhdF70Us X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-18_02,2026-09-16_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 lowpriorityscore=0 priorityscore=1501 spamscore=0 adultscore=0 clxscore=1015 bulkscore=0 malwarescore=0 suspectscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609180117 Let MVIY_PERCPU() calculate the alternative lowcore displacement instead of passing the same value(s) again and again in all percpu inline assemblies. This shortens the inline assemblies and makes them a bit more readable. Signed-off-by: Heiko Carstens --- arch/s390/include/asm/percpu.h | 68 +++++++++++++++------------------- 1 file changed, 29 insertions(+), 39 deletions(-) diff --git a/arch/s390/include/asm/percpu.h b/arch/s390/include/asm/percpu.h index 9888b38dedab..3bc448c4c2dd 100644 --- a/arch/s390/include/asm/percpu.h +++ b/arch/s390/include/asm/percpu.h @@ -99,7 +99,9 @@ * MVIY_ALT(...) <- end of percpu code section */ -#define MVIY_PERCPU(disp, dispalt, reg) \ +#define LC_ALT_ADDR __stringify(LOWCORE_ALT_ADDRESS) + +#define MVIY_PERCPU(disp, reg) \ ".macro GEN_MVIY disp, reg\n" \ ".set .Lreg,255\n" \ ".irp rs,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15\n" \ @@ -112,19 +114,19 @@ ".endif\n" \ "mviy \\disp(%%r0),.Lreg\n" \ ".endm\n" \ - ALTERNATIVE("GEN_MVIY " disp ", " reg "\n", \ - "GEN_MVIY " dispalt ", " reg "\n", \ + ALTERNATIVE("GEN_MVIY " disp " , " reg "\n", \ + "GEN_MVIY " disp "+" LC_ALT_ADDR " , " reg "\n", \ ALT_FEATURE(MFEATURE_LOWCORE)) \ ".purgem GEN_MVIY\n" -#define MVIY_ALT(disp, dispalt) \ - ALTERNATIVE(" mviy " disp "(%%r0),0\n", \ - " mviy " dispalt "(%%r0),0\n", \ +#define MVIY_ALT(disp) \ + ALTERNATIVE(" mviy " disp "(%%r0),0\n", \ + " mviy " disp "+" LC_ALT_ADDR "(%%r0),0\n", \ ALT_FEATURE(MFEATURE_LOWCORE)) -#define AG_ALT(disp, dispalt, reg) \ - ALTERNATIVE(" ag " reg ", " disp "(%%r0)\n", \ - " ag " reg ", " dispalt "(%%r0)\n", \ +#define AG_ALT(disp, reg) \ + ALTERNATIVE(" ag " reg ", " disp "(%%r0)\n", \ + " ag " reg ", " disp "+" LC_ALT_ADDR "(%%r0)\n", \ ALT_FEATURE(MFEATURE_LOWCORE)) #ifndef MARCH_HAS_Z196_FEATURES @@ -153,33 +155,29 @@ do { \ if (__builtin_constant_p(val__) && \ ((szcast)val__ > -129) && ((szcast)val__ < 128)) { \ asm volatile( \ - MVIY_PERCPU("%[disppcpr]", "%[dispaltpcpr]", "%[ptr__]")\ - AG_ALT("%[disppcpo]", "%[dispaltpcpo]", "%[ptr__]") \ + MVIY_PERCPU("%[disppcpr]","%[ptr__]") \ + AG_ALT("%[disppcpo]", "%[ptr__]") \ op2 " 0(%[ptr__]),%[val__]\n" \ - MVIY_ALT("%[disppcpr]", "%[dispaltpcpr]") \ + MVIY_ALT("%[disppcpr]") \ : [ptr__] "+&a" (ptr__), "+m" (*ptr__), \ "=m" (((struct lowcore *)0)->percpu_register) \ : [val__] "i" ((szcast)val__), \ [disppcpr] "i" (lc_pcpr), \ [disppcpo] "i" (lc_pcpo), \ - [dispaltpcpr] "i" (lc_pcpr + LOWCORE_ALT_ADDRESS), \ - [dispaltpcpo] "i" (lc_pcpo + LOWCORE_ALT_ADDRESS), \ "m" (((struct lowcore *)0)->percpu_offset) \ : "cc"); \ } else { \ asm volatile( \ - MVIY_PERCPU("%[disppcpr]", "%[dispaltpcpr]", "%[ptr__]")\ - AG_ALT("%[disppcpo]", "%[dispaltpcpo]", "%[ptr__]") \ + MVIY_PERCPU("%[disppcpr]", "%[ptr__]") \ + AG_ALT("%[disppcpo]", "%[ptr__]") \ op1 " %[old__],%[val__],0(%[ptr__])\n" \ - MVIY_ALT("%[disppcpr]", "%[dispaltpcpr]") \ + MVIY_ALT("%[disppcpr]") \ : [old__] "=&d" (old__), \ [ptr__] "+&a" (ptr__), "+m" (*ptr__), \ "=m" (((struct lowcore *)0)->percpu_register) \ : [val__] "d" (val__), \ [disppcpr] "i" (lc_pcpr), \ [disppcpo] "i" (lc_pcpo), \ - [dispaltpcpr] "i" (lc_pcpr + LOWCORE_ALT_ADDRESS), \ - [dispaltpcpo] "i" (lc_pcpo + LOWCORE_ALT_ADDRESS), \ "m" (((struct lowcore *)0)->percpu_offset) \ : "cc"); \ } \ @@ -199,18 +197,16 @@ do { \ lc_pcpo = offsetof(struct lowcore, percpu_offset); \ ptr__ = PERCPU_PTR(&(pcp)); \ asm_inline volatile( \ - MVIY_PERCPU("%[disppcpr]", "%[dispaltpcpr]", "%[ptr__]")\ - AG_ALT("%[disppcpo]", "%[dispaltpcpo]", "%[ptr__]") \ + MVIY_PERCPU("%[disppcpr]","%[ptr__]") \ + AG_ALT("%[disppcpo]","%[ptr__]") \ op " %[old__],%[val__],0(%[ptr__])\n" \ - MVIY_ALT("%[disppcpr]", "%[dispaltpcpr]") \ + MVIY_ALT("%[disppcpr]") \ : [old__] "=&d" (old__), \ [ptr__] "+&a" (ptr__), "+m" (*ptr__), \ "=m" (((struct lowcore *)0)->percpu_register) \ : [val__] "d" (val__), \ [disppcpr] "i" (lc_pcpr), \ [disppcpo] "i" (lc_pcpo), \ - [dispaltpcpr] "i" (lc_pcpr + LOWCORE_ALT_ADDRESS), \ - [dispaltpcpo] "i" (lc_pcpo + LOWCORE_ALT_ADDRESS), \ "m" (((struct lowcore *)0)->percpu_offset) \ : "cc"); \ old__ + val__; \ @@ -230,18 +226,16 @@ do { \ lc_pcpo = offsetof(struct lowcore, percpu_offset); \ ptr__ = PERCPU_PTR(&(pcp)); \ asm_inline volatile( \ - MVIY_PERCPU("%[disppcpr]", "%[dispaltpcpr]", "%[ptr__]")\ - AG_ALT("%[disppcpo]", "%[dispaltpcpo]", "%[ptr__]") \ + MVIY_PERCPU("%[disppcpr]","%[ptr__]") \ + AG_ALT("%[disppcpo]","%[ptr__]") \ op " %[old__],%[val__],0(%[ptr__])\n" \ - MVIY_ALT("%[disppcpr]", "%[dispaltpcpr]") \ + MVIY_ALT("%[disppcpr]") \ : [old__] "=&d" (old__), \ [ptr__] "+&a" (ptr__), "+m" (*ptr__), \ "=m" (((struct lowcore *)0)->percpu_register) \ : [val__] "d" (val__), \ [disppcpr] "i" (lc_pcpr), \ [disppcpo] "i" (lc_pcpo), \ - [dispaltpcpr] "i" (lc_pcpr + LOWCORE_ALT_ADDRESS), \ - [dispaltpcpo] "i" (lc_pcpo + LOWCORE_ALT_ADDRESS), \ "m" (((struct lowcore *)0)->percpu_offset) \ : "cc"); \ } while (0) @@ -263,16 +257,14 @@ do { \ lc_pcpo = offsetof(struct lowcore, percpu_offset); \ ptr__ = PERCPU_PTR(&(pcp)); \ asm_inline volatile( \ - MVIY_PERCPU("%[disppcpr]", "%[dispaltpcpr]", "%[ptr__]")\ - AG_ALT("%[disppcpo]", "%[dispaltpcpo]", "%[ptr__]") \ + MVIY_PERCPU("%[disppcpr]","%[ptr__]") \ + AG_ALT("%[disppcpo]","%[ptr__]") \ op " %[res__],0(%[ptr__])\n" \ - MVIY_ALT("%[disppcpr]", "%[dispaltpcpr]") \ + MVIY_ALT("%[disppcpr]") \ : [res__] "=&d" (res__), [ptr__] "+&a" (ptr__), \ "=m" (((struct lowcore *)0)->percpu_register) \ : [disppcpr] "i" (lc_pcpr), \ [disppcpo] "i" (lc_pcpo), \ - [dispaltpcpr] "i" (lc_pcpr + LOWCORE_ALT_ADDRESS), \ - [dispaltpcpo] "i" (lc_pcpo + LOWCORE_ALT_ADDRESS), \ "m" (*ptr__), \ "m" (((struct lowcore *)0)->percpu_offset) \ : "cc"); \ @@ -294,17 +286,15 @@ do { \ lc_pcpo = offsetof(struct lowcore, percpu_offset); \ ptr__ = PERCPU_PTR(&(pcp)); \ asm_inline volatile( \ - MVIY_PERCPU("%[disppcpr]", "%[dispaltpcpr]", "%[ptr__]")\ - AG_ALT("%[disppcpo]", "%[dispaltpcpo]", "%[ptr__]") \ + MVIY_PERCPU("%[disppcpr]","%[ptr__]") \ + AG_ALT("%[disppcpo]","%[ptr__]") \ op " %[val__],0(%[ptr__])\n" \ - MVIY_ALT("%[disppcpr]", "%[dispaltpcpr]") \ + MVIY_ALT("%[disppcpr]") \ : [ptr__] "+&a" (ptr__), "=m" (*ptr__), \ "=m" (((struct lowcore *)0)->percpu_register) \ : [val__] "d" (val__), \ [disppcpr] "i" (lc_pcpr), \ [disppcpo] "i" (lc_pcpo), \ - [dispaltpcpr] "i" (lc_pcpr + LOWCORE_ALT_ADDRESS), \ - [dispaltpcpo] "i" (lc_pcpo + LOWCORE_ALT_ADDRESS), \ "m" (((struct lowcore *)0)->percpu_offset) \ : "cc"); \ } while (0) -- 2.53.0