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client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by CH2PEPF00000145.mail.protection.outlook.com (10.167.244.102) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.451.8 via Frontend Transport; Fri, 18 Sep 2026 14:56:53 +0000 Received: from quartz-7b1chost.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.49; Fri, 18 Sep 2026 09:56:51 -0500 From: Yazen Ghannam To: CC: , , , , Yazen Ghannam Subject: [PATCH v2 06/10] PCI/portdrv: Group PCI Exp Cap services into a single mask Date: Fri, 18 Sep 2026 09:56:14 -0500 Message-ID: <20260918145619.3016889-7-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260918145619.3016889-1-yazen.ghannam@amd.com> References: <20260918145619.3016889-1-yazen.ghannam@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF00000145:EE_|CH3PR12MB9316:EE_ X-MS-Office365-Filtering-Correlation-Id: fa0d1c9a-6ad5-4f67-0238-08df15951389 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|82310400026|36860700016|23010399003|22082099003|18002099003|11063799006|10067099003|56012099006; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: OMDxV4g9SDntZx/oOgNoBTNFQI6PzNYx6W6fsc/Z/aORyYaLuCv9NvKkfjhSWMZbk4EtX5bQkzQgBCaA+hhdVk+JzK4YUH8I9SJFOj50MElcR1Wc149oI9Yq26stHCnRRAuB//OBzFp0w5pJ8YrQ7yN6gE4OeO+XXN4EU2vDcU2U3TNz3YGT6GxgzlSEJuJqNMuUSeKanro2iGIspHEW9/BgjXEHv+z4H65LeBu6ynSJ9DwS39ixvZMZDKTDfLZi7k1YZgT6+OC+K+5Cu8H0FDc61eaNzYzuLiaeeB7vXiE94ylCdL3CZD/o0k5USPsiUTSR5u/FpNOKnYSY5azbrwTRjzDjJH/icDBKs/vQNmgV76cBcqAtwMk+KmWNfpj/qNdDcMNE35xgSyAiTvpmFgfHbZU1+oq6DU94HBqlXOXJfs+eYMYuGdHYfD8CTY3v X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Sep 2026 14:56:53.1401 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fa0d1c9a-6ad5-4f67-0238-08df15951389 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000145.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9316 PME, hotplug, and bandwidth notification are all services of the PCI Express Capability and share a single MSI/MSI-X interrupt vector. The set of these services is open-coded as a bitmask in more than one place. That is repetitive and easy to get out of sync as services are added. Define a single PCIE_PORT_SERVICES_EXPCAP mask beside the service bits it groups, and use it in place of the open-coded expressions. Assign the shared vector by iterating the mask rather than naming each service again, so adding one is a single edit. Iterating narrows which irqs[] entries get written. The open-coded version filled the slot of every service in the group as soon as one of them was in the mask. Those extra entries were never read, since pcie_init_service_irqs() presets the array to -1 and pcie_port_device_register() only reads the slot of a service it found. No functional change intended. Assisted-by: LLM Signed-off-by: Yazen Ghannam --- drivers/pci/pcie/portdrv.c | 16 ++++++++-------- drivers/pci/pcie/portdrv.h | 5 +++++ 2 files changed, 13 insertions(+), 8 deletions(-) diff --git a/drivers/pci/pcie/portdrv.c b/drivers/pci/pcie/portdrv.c index a9cbfc1d2bc7..ca1b9dbb8b08 100644 --- a/drivers/pci/pcie/portdrv.c +++ b/drivers/pci/pcie/portdrv.c @@ -67,8 +67,7 @@ static int pcie_message_numbers(struct pci_dev *dev, int mask, * 7.8.2, 7.10.10, 7.31.2. */ - if (mask & (PCIE_PORT_SERVICE_PME | PCIE_PORT_SERVICE_HP | - PCIE_PORT_SERVICE_BWCTRL)) { + if (mask & PCIE_PORT_SERVICES_EXPCAP) { pcie_capability_read_word(dev, PCI_EXP_FLAGS, ®16); *pme = FIELD_GET(PCI_EXP_FLAGS_IRQ, reg16); nvec = *pme + 1; @@ -114,6 +113,8 @@ static int pcie_port_enable_irq_vec(struct pci_dev *dev, int *irqs, int mask) { int nr_entries, nvec, pcie_irq; u32 pme = 0, aer = 0, dpc = 0; + unsigned long expcap; + unsigned int i; /* Allocate the maximum possible number of MSI/MSI-X vectors */ nr_entries = pci_alloc_irq_vectors(dev, 1, PCIE_PORT_MAX_MSI_ENTRIES, @@ -148,13 +149,12 @@ static int pcie_port_enable_irq_vec(struct pci_dev *dev, int *irqs, int mask) return nr_entries; } - /* PME, hotplug and bandwidth notification share an MSI/MSI-X vector */ - if (mask & (PCIE_PORT_SERVICE_PME | PCIE_PORT_SERVICE_HP | - PCIE_PORT_SERVICE_BWCTRL)) { + /* These services share the PCIe Capability Interrupt Message Number */ + expcap = mask & PCIE_PORT_SERVICES_EXPCAP; + if (expcap) { pcie_irq = pci_irq_vector(dev, pme); - irqs[PCIE_PORT_SERVICE_PME_SHIFT] = pcie_irq; - irqs[PCIE_PORT_SERVICE_HP_SHIFT] = pcie_irq; - irqs[PCIE_PORT_SERVICE_BWCTRL_SHIFT] = pcie_irq; + for_each_set_bit(i, &expcap, PCIE_PORT_DEVICE_MAXSERVICES) + irqs[i] = pcie_irq; } if (mask & PCIE_PORT_SERVICE_AER) diff --git a/drivers/pci/pcie/portdrv.h b/drivers/pci/pcie/portdrv.h index cc58bf2f2c84..bf18ca415990 100644 --- a/drivers/pci/pcie/portdrv.h +++ b/drivers/pci/pcie/portdrv.h @@ -23,6 +23,11 @@ #define PCIE_PORT_SERVICE_BWCTRL_SHIFT 4 /* Bandwidth Controller (notifications) */ #define PCIE_PORT_SERVICE_BWCTRL (1 << PCIE_PORT_SERVICE_BWCTRL_SHIFT) +/* Services sharing the PCI Express Capability Interrupt Message Number */ +#define PCIE_PORT_SERVICES_EXPCAP (PCIE_PORT_SERVICE_PME | \ + PCIE_PORT_SERVICE_HP | \ + PCIE_PORT_SERVICE_BWCTRL) + #define PCIE_PORT_DEVICE_MAXSERVICES 5 extern bool pcie_ports_dpc_native; -- 2.43.0