From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail.cjdns.fr (mail.cjdns.fr [5.135.140.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 213F850B403; Fri, 18 Sep 2026 15:36:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.135.140.105 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789745791; cv=none; b=piZUGp+Hmwp3tr42ReJUfFfEaQGvysWJR8JsF5aF4JDECJr/lQyKL4t6lJDaJYPPSlTD6jnrdZ18u5IpP4wy2Q6lLQ2+0kcN15UZyw1TAWDoAq6ZJJJX9xAicDq0nuu81XzeEbP2r/KhXJmJyBNatpPyX0cFJHIQPnmtvnOwT04= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789745791; c=relaxed/simple; bh=x0XMny1qGGl4AJoowktjLCWIaQ/7L5RzSu5rS1V5VRE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=QTj1+bhJVp0vQaFbHQpYC9AWW67MiFZbNaE9ySIm1kG9NrQaNSg8zThtt43DCRM22SEXjCIAGHID7W4+ZOIH2eZcGh095EU74w2+aax4mdw2l98Nv7lWNs0wWBK5Be7hbENU7xXJ6DqjiQwqqvrKNjpdinS/bkI1b0veyA02GLE= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr; spf=none smtp.mailfrom=cjdns.fr; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b=vw7SD2oJ; arc=none smtp.client-ip=5.135.140.105 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b="vw7SD2oJ" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 409574E0025; Fri, 18 Sep 2026 17:36:25 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cjdns.fr; s=dkim; t=1789745787; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=lRhqM7LAgl/X+6g5+JRRCWTiassQyFmX1v5QtTJrszQ=; b=vw7SD2oJG1EOTBIe4kPOT7F3IJvmTXNbwU7ID0V4Z4BwLupmlW/F800kAy409GWzTqbz39 axcB1MES6KkVcgYL/aHzFQ4UH6fXFM2BIBuHtbFdC9LEez9Zc0E4wC4hgFkkINUSy8wike kBwxq1WU1fvTKH7X++zXgjMKNztL8+8mTeF+Q9Id16VSXNYStbL3U3lokeTqukeCdm3qre Qd6+dcPGXYk7D9rKuE/Xsnd2SSOh90Ohf8MO0KAUdUS6tsSDtxSBnIes+3GsC+8mB7WwIl h7y7UG9tFEdqqbekPJkXzqJuAMRDZsN7yECJqXpC5hG0upqT4X+RPlDHVob2Zg== From: Caleb James DeLisle To: linux-mips@vger.kernel.org Cc: conor+dt@kernel.org, daniel.lezcano@kernel.org, devicetree@vger.kernel.org, krzk+dt@kernel.org, linux-kernel@vger.kernel.org, naseefkm@gmail.com, robh@kernel.org, tglx@kernel.org, grandmaster@al2klimov.de, Caleb James DeLisle Subject: [PATCH v9 4/5] clocksource/timer-econet-en751221: Disable IRQ until cevt registered Date: Fri, 18 Sep 2026 15:36:05 +0000 Message-Id: <20260918153606.344143-5-cjd@cjdns.fr> In-Reply-To: <20260918153606.344143-1-cjd@cjdns.fr> References: <20260918153606.344143-1-cjd@cjdns.fr> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Last-TLS-Session-Version: TLSv1.3 Eliminate a race condition where cevt_interrupt may trigger before clockevents_config_and_register has been called, and dev->event_handler is at that point NULL. Additionally, NULL check dev->event_handler in interrupt callback just in case clockevents_config_and_register failed. Signed-off-by: Caleb James DeLisle --- drivers/clocksource/timer-econet-en751221.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/clocksource/timer-econet-en751221.c b/drivers/clocksource/timer-econet-en751221.c index 714702b9ef12..f2c4c1ee0a56 100644 --- a/drivers/clocksource/timer-econet-en751221.c +++ b/drivers/clocksource/timer-econet-en751221.c @@ -75,7 +75,10 @@ static irqreturn_t cevt_interrupt(int irq, void *dev_id) return IRQ_NONE; iowrite32(ioread32(reg_count(cpu)), reg_compare(cpu)); - dev->event_handler(dev); + + if (dev->event_handler) + dev->event_handler(dev); + return IRQ_HANDLED; } @@ -104,12 +107,11 @@ static int cevt_init_cpu(uint cpu) reg = ioread32(reg_ctl(cpu)) | ctl_bit_enabled(cpu); iowrite32(reg, reg_ctl(cpu)); - enable_percpu_irq(cd->irq, IRQ_TYPE_NONE); - - /* Do this last because it synchronously configures the timer */ clockevents_config_and_register(cd, econet_timer.freq_hz, ECONET_MIN_DELTA, ECONET_MAX_DELTA); + enable_percpu_irq(cd->irq, IRQ_TYPE_NONE); + return 0; } @@ -178,6 +180,8 @@ static int __init timer_init(struct device_node *np) goto out_membase; } + irq_set_status_flags(econet_timer.irq, IRQ_NOAUTOEN); + ret = request_percpu_irq(econet_timer.irq, cevt_interrupt, np->name, &econet_timer_pcpu); -- 2.39.5