From: Luca Leonardo Scorcia <l.scorcia@gmail.com>
To: linux-mediatek@lists.infradead.org
Cc: Luca Leonardo Scorcia <l.scorcia@gmail.com>,
Chun-Kuang Hu <chunkuang.hu@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
Maxime Ripard <mripard@kernel.org>,
Thomas Zimmermann <tzimmermann@suse.de>,
David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>,
CK Hu <ck.hu@mediatek.com>, Jitao shi <jitao.shi@mediatek.com>,
dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH 3/4] soc: mediatek: mt8167-mmsys: add routes for all display paths
Date: Fri, 18 Sep 2026 19:55:27 +0200 [thread overview]
Message-ID: <20260918175736.355305-4-l.scorcia@gmail.com> (raw)
In-Reply-To: <20260918175736.355305-1-l.scorcia@gmail.com>
mt8167 display output pipeline can be configured in many different ways.
Add support for additional routes according to the SoC data sheet and
Android sources. There's a few inconsistencies between those two, but
assume the Android sources are correct since they are required to drive
HDMI output via DPI1.
Signed-off-by: Luca Leonardo Scorcia <l.scorcia@gmail.com>
---
drivers/soc/mediatek/mt8167-mmsys.h | 183 ++++++++++++++++++++++++++--
1 file changed, 174 insertions(+), 9 deletions(-)
diff --git a/drivers/soc/mediatek/mt8167-mmsys.h b/drivers/soc/mediatek/mt8167-mmsys.h
index 001379373507..aab1774152c5 100644
--- a/drivers/soc/mediatek/mt8167-mmsys.h
+++ b/drivers/soc/mediatek/mt8167-mmsys.h
@@ -5,35 +5,200 @@
#define MT8167_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x030
#define MT8167_DISP_REG_CONFIG_DISP_DITHER_MOUT_EN 0x038
+#define MT8167_DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x03c
#define MT8167_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x058
+#define MT8167_DISP_REG_CONFIG_DISP_WDMA0_SEL_IN 0x05c
+#define MT8167_DISP_REG_CONFIG_DISP_UFOE_SEL_IN 0x060
#define MT8167_DISP_REG_CONFIG_DISP_DSI0_SEL_IN 0x064
+#define MT8167_DISP_REG_CONFIG_DISP_DPI0_SEL_IN 0x068
#define MT8167_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN 0x06c
+#define MT8167_DISP_REG_CONFIG_DISP_RDMA1_SOUT_SEL_IN 0x070
+#define MT8167_DISP_REG_CONFIG_DISP_DPI1_SEL_IN 0x074
+
+#define MT8167_OVL0_MOUT_EN_COLOR0 0x1
+#define MT8167_OVL0_MOUT_EN_WDMA0 0x2
+#define MT8167_OVL0_MOUT_EN_MASK 0x3
#define MT8167_DITHER_MOUT_EN_RDMA0 0x1
+#define MT8167_DITHER_MOUT_EN_UFOE 0x2
+#define MT8167_DITHER_MOUT_EN_WDMA0 0x4
#define MT8167_DITHER_MOUT_EN_MASK 0x7
-#define MT8167_RDMA0_SOUT_DSI0 0x2
-#define MT8167_RDMA0_SOUT_MASK 0x3
+#define MT8167_UFOE_MOUT_EN_DSI0 0x1
+#define MT8167_UFOE_MOUT_EN_DPI0 0x2
+/*
+ * For some reason Android sources and the data sheet don't agree here,
+ * the data sheet has UFOE_MOUT_EN_WDMA0 as 0x4 and does not mention DPI1.
+ */
+#define MT8167_UFOE_MOUT_EN_DPI1 0x4
+#define MT8167_UFOE_MOUT_EN_WDMA0 0x8
+#define MT8167_UFOE_MOUT_EN_MASK 0xF
+
+#define MT8167_COLOR0_SEL_IN_RDMA0 0x0
+#define MT8167_COLOR0_SEL_IN_OVL0 0x1
+#define MT8167_COLOR0_SEL_IN_MASK 0x1
+
+#define MT8167_WDMA0_SEL_IN_OVL0 0x0
+#define MT8167_WDMA0_SEL_IN_DITHER 0x1
+#define MT8167_WDMA0_SEL_IN_UFOE 0x2
+#define MT8167_WDMA0_SEL_IN_MASK 0x3
+
+#define MT8167_UFOE_SEL_IN_RDMA0 0x0
+#define MT8167_UFOE_SEL_IN_DITHER 0x1
+#define MT8167_UFOE_SEL_IN_MASK 0x1
+#define MT8167_DSI0_SEL_IN_UFOE 0x0
#define MT8167_DSI0_SEL_IN_RDMA0 0x1
+#define MT8167_DSI0_SEL_IN_RDMA1 0x2
#define MT8167_DSI0_SEL_IN_MASK 0x3
+#define MT8167_DPI0_SEL_IN_UFOE 0x0
+#define MT8167_DPI0_SEL_IN_RDMA0 0x1
+#define MT8167_DPI0_SEL_IN_RDMA1 0x2
+#define MT8167_DPI0_SEL_IN_MASK 0x3
+
+#define MT8167_DPI1_SEL_IN_UFOE 0x0
+#define MT8167_DPI1_SEL_IN_RDMA0 0x1
+#define MT8167_DPI1_SEL_IN_RDMA1 0x2
+#define MT8167_DPI1_SEL_IN_MASK 0x3
+
+#define MT8167_RDMA0_SOUT_UFOE 0x0
+#define MT8167_RDMA0_SOUT_COLOR0 0x1
+#define MT8167_RDMA0_SOUT_DSI0 0x2
+#define MT8167_RDMA0_SOUT_DPI0 0x3
+/* DPI1 is only defined in Android sources, not in the data sheet */
+#define MT8167_RDMA0_SOUT_DPI1 0x4
+#define MT8167_RDMA0_SOUT_MASK 0x7
+
+#define MT8167_RDMA1_SOUT_DSI0 0x0
+#define MT8167_RDMA1_SOUT_DPI0 0x1
+/* DPI1 is only defined in Android sources, not in the data sheet */
+#define MT8167_RDMA1_SOUT_DPI1 0x2
+#define MT8167_RDMA1_SOUT_MASK 0x3
+
static const struct mtk_mmsys_routes mt8167_mmsys_routing_table[] = {
+ /* OVL0<->COLOR0 */
MMSYS_ROUTE(OVL, 0, COLOR, 0,
- MT8167_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_COLOR0,
- OVL0_MOUT_EN_COLOR0),
+ MT8167_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, MT8167_OVL0_MOUT_EN_MASK,
+ MT8167_OVL0_MOUT_EN_COLOR0),
+ MMSYS_ROUTE(OVL, 0, COLOR, 0,
+ MT8167_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, MT8167_COLOR0_SEL_IN_MASK,
+ MT8167_COLOR0_SEL_IN_OVL0),
+
+ /* OVL0<->WDMA0 */
+ MMSYS_ROUTE(OVL, 0, WDMA, 0,
+ MT8167_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, MT8167_OVL0_MOUT_EN_MASK,
+ MT8167_OVL0_MOUT_EN_WDMA0),
+ MMSYS_ROUTE(OVL, 0, WDMA, 0,
+ MT8167_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, MT8167_COLOR0_SEL_IN_MASK,
+ MT8167_WDMA0_SEL_IN_OVL0),
+
+ /* DITHER0 outputs */
MMSYS_ROUTE(DITHER, 0, RDMA, 0,
MT8167_DISP_REG_CONFIG_DISP_DITHER_MOUT_EN, MT8167_DITHER_MOUT_EN_MASK,
MT8167_DITHER_MOUT_EN_RDMA0),
- MMSYS_ROUTE(OVL, 0, COLOR, 0,
- MT8167_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, COLOR0_SEL_IN_OVL0,
- COLOR0_SEL_IN_OVL0),
- MMSYS_ROUTE(RDMA, 0, DSI, 0,
+ MMSYS_ROUTE(DITHER, 0, UFOE, 0,
+ MT8167_DISP_REG_CONFIG_DISP_DITHER_MOUT_EN, MT8167_DITHER_MOUT_EN_MASK,
+ MT8167_DITHER_MOUT_EN_UFOE),
+ MMSYS_ROUTE(DITHER, 0, WDMA, 0,
+ MT8167_DISP_REG_CONFIG_DISP_DITHER_MOUT_EN, MT8167_DITHER_MOUT_EN_MASK,
+ MT8167_DITHER_MOUT_EN_WDMA0),
+
+ /* UFOE<->DSI0 */
+ MMSYS_ROUTE(UFOE, 0, DSI, 0,
+ MT8167_DISP_REG_CONFIG_DISP_UFOE_MOUT_EN, MT8167_UFOE_MOUT_EN_MASK,
+ MT8167_UFOE_MOUT_EN_DSI0),
+ MMSYS_ROUTE(UFOE, 0, DSI, 0,
MT8167_DISP_REG_CONFIG_DISP_DSI0_SEL_IN, MT8167_DSI0_SEL_IN_MASK,
- MT8167_DSI0_SEL_IN_RDMA0),
+ MT8167_DSI0_SEL_IN_UFOE),
+
+ /* UFOE<->DPI0 */
+ MMSYS_ROUTE(UFOE, 0, DPI, 0,
+ MT8167_DISP_REG_CONFIG_DISP_UFOE_MOUT_EN, MT8167_UFOE_MOUT_EN_MASK,
+ MT8167_UFOE_MOUT_EN_DPI0),
+ MMSYS_ROUTE(UFOE, 0, DPI, 0,
+ MT8167_DISP_REG_CONFIG_DISP_DPI0_SEL_IN, MT8167_DPI0_SEL_IN_MASK,
+ MT8167_DPI0_SEL_IN_UFOE),
+
+ /* UFOE<->DPI1 */
+ MMSYS_ROUTE(UFOE, 0, DPI, 1,
+ MT8167_DISP_REG_CONFIG_DISP_UFOE_MOUT_EN, MT8167_UFOE_MOUT_EN_MASK,
+ MT8167_UFOE_MOUT_EN_DPI1),
+ MMSYS_ROUTE(UFOE, 0, DPI, 1,
+ MT8167_DISP_REG_CONFIG_DISP_DPI1_SEL_IN, MT8167_DPI1_SEL_IN_MASK,
+ MT8167_DPI1_SEL_IN_UFOE),
+
+ /* UFOE<->WDMA0 */
+ MMSYS_ROUTE(UFOE, 0, WDMA, 0,
+ MT8167_DISP_REG_CONFIG_DISP_UFOE_MOUT_EN, MT8167_UFOE_MOUT_EN_MASK,
+ MT8167_UFOE_MOUT_EN_WDMA0),
+ MMSYS_ROUTE(UFOE, 0, WDMA, 0,
+ MT8167_DISP_REG_CONFIG_DISP_WDMA0_SEL_IN, MT8167_WDMA0_SEL_IN_MASK,
+ MT8167_WDMA0_SEL_IN_UFOE),
+
+ /* RDMA0<->UFOE */
+ MMSYS_ROUTE(RDMA, 0, UFOE, 0,
+ MT8167_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN, MT8167_RDMA0_SOUT_MASK,
+ MT8167_RDMA0_SOUT_UFOE),
+ MMSYS_ROUTE(RDMA, 0, UFOE, 0,
+ MT8167_DISP_REG_CONFIG_DISP_UFOE_SEL_IN, MT8167_UFOE_SEL_IN_MASK,
+ MT8167_UFOE_SEL_IN_RDMA0),
+
+ /* RDMA0->COLOR0 */
+ MMSYS_ROUTE(RDMA, 0, COLOR, 0,
+ MT8167_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN, MT8167_RDMA0_SOUT_MASK,
+ MT8167_RDMA0_SOUT_COLOR0),
+ MMSYS_ROUTE(RDMA, 0, COLOR, 0,
+ MT8167_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, MT8167_COLOR0_SEL_IN_MASK,
+ MT8167_COLOR0_SEL_IN_RDMA0),
+
+ /* RDMA0<->DSI0 */
MMSYS_ROUTE(RDMA, 0, DSI, 0,
MT8167_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN, MT8167_RDMA0_SOUT_MASK,
MT8167_RDMA0_SOUT_DSI0),
+ MMSYS_ROUTE(RDMA, 0, DSI, 0,
+ MT8167_DISP_REG_CONFIG_DISP_DSI0_SEL_IN, MT8167_DSI0_SEL_IN_MASK,
+ MT8167_DSI0_SEL_IN_RDMA0),
+
+ /* RDMA0<->DPI0 */
+ MMSYS_ROUTE(RDMA, 0, DPI, 0,
+ MT8167_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN, MT8167_RDMA0_SOUT_MASK,
+ MT8167_RDMA0_SOUT_DPI0),
+ MMSYS_ROUTE(RDMA, 0, DPI, 0,
+ MT8167_DISP_REG_CONFIG_DISP_DPI0_SEL_IN, MT8167_DPI0_SEL_IN_MASK,
+ MT8167_DPI0_SEL_IN_RDMA0),
+
+ /* RDMA0<->DPI1 */
+ MMSYS_ROUTE(RDMA, 0, DPI, 1,
+ MT8167_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN, MT8167_RDMA0_SOUT_MASK,
+ MT8167_RDMA0_SOUT_DPI1),
+ MMSYS_ROUTE(RDMA, 0, DPI, 1,
+ MT8167_DISP_REG_CONFIG_DISP_DPI1_SEL_IN, MT8167_DPI1_SEL_IN_MASK,
+ MT8167_DPI1_SEL_IN_RDMA0),
+
+ /* RDMA1<->DSI0 */
+ MMSYS_ROUTE(RDMA, 1, DSI, 0,
+ MT8167_DISP_REG_CONFIG_DISP_RDMA1_SOUT_SEL_IN, MT8167_RDMA1_SOUT_MASK,
+ MT8167_RDMA1_SOUT_DSI0),
+ MMSYS_ROUTE(RDMA, 1, DPI, 0,
+ MT8167_DISP_REG_CONFIG_DISP_DSI0_SEL_IN, MT8167_DSI0_SEL_IN_MASK,
+ MT8167_DPI0_SEL_IN_RDMA1),
+
+ /* RDMA1<->DPI0 */
+ MMSYS_ROUTE(RDMA, 1, DPI, 0,
+ MT8167_DISP_REG_CONFIG_DISP_RDMA1_SOUT_SEL_IN, MT8167_RDMA1_SOUT_MASK,
+ MT8167_RDMA1_SOUT_DPI0),
+ MMSYS_ROUTE(RDMA, 1, DPI, 0,
+ MT8167_DISP_REG_CONFIG_DISP_DPI0_SEL_IN, MT8167_DPI0_SEL_IN_MASK,
+ MT8167_DPI0_SEL_IN_RDMA1),
+
+ /* RDMA1<->DPI1 */
+ MMSYS_ROUTE(RDMA, 1, DPI, 1,
+ MT8167_DISP_REG_CONFIG_DISP_RDMA1_SOUT_SEL_IN, MT8167_RDMA1_SOUT_MASK,
+ MT8167_RDMA1_SOUT_DPI1),
+ MMSYS_ROUTE(RDMA, 1, DPI, 1,
+ MT8167_DISP_REG_CONFIG_DISP_DPI1_SEL_IN, MT8167_DPI1_SEL_IN_MASK,
+ MT8167_DPI1_SEL_IN_RDMA1),
};
#endif /* __SOC_MEDIATEK_MT8167_MMSYS_H */
--
2.43.0
next prev parent reply other threads:[~2026-09-18 17:57 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-18 17:55 [PATCH 0/4] Add support for the mt8167 display pipeline Luca Leonardo Scorcia
2026-09-18 17:55 ` [PATCH 1/4] dt-bindings: display: mediatek: dpi: Add compatible for mt8167 Luca Leonardo Scorcia
2026-09-18 17:55 ` [PATCH 2/4] drm/mediatek: Add support for mt8167 Digital Parallel Interface Luca Leonardo Scorcia
2026-09-18 17:55 ` Luca Leonardo Scorcia [this message]
2026-09-18 18:29 ` [PATCH 3/4] soc: mediatek: mt8167-mmsys: add routes for all display paths Luca Leonardo Scorcia
2026-09-18 17:55 ` [PATCH 4/4] arm64: dts: mediatek: mt8167: Add DRM nodes Luca Leonardo Scorcia
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