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Instead of programming a fake register bit (BIT(0) of TEST1, while the QUSB2 platforms on that platform should use BIT(3) of TEST_CTRL), explicitly disable autoresume programming on these devices via the flag in the platform data. Fixes: 2cfbe6765b7a ("phy: qcom-qusb2: add QUSB2 support for IPQ6018") Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Signed-off-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-qusb2.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c b/drivers/phy/qualcomm/phy-qcom-qusb2.c index fc516b7cf5fa..a1de05a83128 100644 --- a/drivers/phy/qualcomm/phy-qcom-qusb2.c +++ b/drivers/phy/qualcomm/phy-qcom-qusb2.c @@ -294,6 +294,7 @@ struct qusb2_phy_cfg { unsigned int mask_core_ready; unsigned int disable_ctrl; unsigned int autoresume_en; + bool autoresume_disable; /* true if PHY has PLL_TEST register to select clk_scheme */ bool has_pll_test; @@ -341,6 +342,7 @@ static const struct qusb2_phy_cfg ipq6018_phy_cfg = { .disable_ctrl = POWER_DOWN, .mask_core_ready = PLL_LOCKED, /* autoresume not used */ + .autoresume_disable = true, .autoresume_en = BIT(0), }; @@ -687,7 +689,7 @@ static int __maybe_unused qusb2_phy_runtime_suspend(struct device *dev) } /* enable phy auto-resume only if device is connected on bus */ - if (qphy->mode != PHY_MODE_INVALID) { + if (qphy->mode != PHY_MODE_INVALID && !cfg->autoresume_disable) { qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1], cfg->autoresume_en); /* Autoresume bit has to be toggled in order to enable it */ -- 2.47.3