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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-33c331d3f2csm14091444eec.28.2026.09.20.23.20.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Sep 2026 23:20:21 -0700 (PDT) From: Kathiravan Thirumoorthy Date: Mon, 21 Sep 2026 11:49:38 +0530 Subject: [PATCH 05/11] dt-bindings: clock: qcom: ipq5332-gcc: Describe clock inputs per compatible Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260921-ipq_clk_changes-v1-5-d242e3d49648@oss.qualcomm.com> References: <20260921-ipq_clk_changes-v1-0-d242e3d49648@oss.qualcomm.com> In-Reply-To: <20260921-ipq_clk_changes-v1-0-d242e3d49648@oss.qualcomm.com> To: Bjorn Andersson , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Georgi Djakov , Konrad Dybcio , Varadarajan Narayanan , Dmitry Baryshkov , Abel Vesa , Gokul Sriram Palanisamy , Sricharan Ramabadhran , Kathiravan T Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, Kathiravan Thirumoorthy X-Mailer: b4 0.15.2 X-Authority-Analysis: v=2.4 cv=HIZWhYtv c=1 sm=1 tr=0 ts=6ab0cca7 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=GdSppTGlZM03nT4b0GsA:9 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwOTIxMDA4OSBTYWx0ZWRfX2ro+70uLwqBJ mpkVzjUc/85QNwIyeMfroAk8fEeLjGOHGDPRd4YGFR5QIlc98eYVSKfEc8yIxAE7tfF/E4YmLXw uK5f2Mhn7+LezwcYC6V9dZkwgEqlAuI= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTIxMDA4OSBTYWx0ZWRfX+W1vPSH+ytae kYhjegQR/XuisOdLoCmwHJ0JIebaPiVPZb8G9MqxLjQ/VF4vHe6idtZAn/2tVFi26I/9pX3H0vy NaVX9OwMOXTt37jXt0u+39Upcm8gmosgMtaPrGxOa1SIFnwcMqTF62gRg/DaItoqBFDt8LrH9e/ Qcdb1/s1Krw6jI/1XBCcHh2G7S30AVpQMhfJlfe15xWfnQt1K/J4hs2bxfoXbYOaHlXbLjWQWtW yCqFChFXkR4uW+p5eMyPAuEc5hsfmIJKDU/aJY37DwzfY2GizN2cjRHR+ew7sN8WYfV7YGFlBQG 2R5QXl++buQZfI1RP69EECFIMrQBXUeTESNYzrq//z32s2JReVL4pBCAQGqhkwXMyZm+RXaSEzg 8CRT98/cUG9mMjYEM7P9vxvVFhO3Kk9ks2aFJB3WCsYz6n01L+Yjm+c6sqarq9c271jXeJAmK5W V14klZUlNdIxQbWl/jA== X-Proofpoint-ORIG-GUID: DrfjVdgVwtme3-EaC9OBGLvZKkO1i90i X-Proofpoint-GUID: DrfjVdgVwtme3-EaC9OBGLvZKkO1i90i X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-21_02,2026-09-16_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 malwarescore=0 adultscore=0 lowpriorityscore=0 bulkscore=0 spamscore=0 priorityscore=1501 suspectscore=0 phishscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609210089 The IPQ5332 and IPQ5424 GCC blocks use different clock input orderings. Document the clock inputs in compatible-specific schema constraints instead of using a common clock description. Also add the 375 MHz PPE clock generated by the CMN PLL to the IPQ5424 clock input list. This keeps the binding aligned with the clock ordering used by the existing DTS and GCC driver implementations. Signed-off-by: Kathiravan Thirumoorthy --- .../bindings/clock/qcom,ipq5332-gcc.yaml | 26 +++++++++++++--------- 1 file changed, 16 insertions(+), 10 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml index 1230183fc0a9..fb39dffca988 100644 --- a/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml @@ -25,14 +25,7 @@ properties: clocks: minItems: 5 - items: - - description: Board XO clock source - - description: Sleep clock source - - description: PCIE 2lane PHY pipe clock source - - description: PCIE 2lane x1 PHY pipe clock source (For second lane) - - description: USB PCIE wrapper pipe clock source - - description: PCIE 2-lane PHY2 pipe clock source - - description: PCIE 2-lane PHY3 pipe clock source + maxItems: 8 '#power-domain-cells': false '#interconnect-cells': @@ -52,7 +45,12 @@ allOf: then: properties: clocks: - maxItems: 5 + items: + - description: Board XO clock source + - description: Sleep clock source + - description: PCIE 2lane PHY pipe clock source + - description: PCIE 2lane x1 PHY pipe clock source (For second lane) + - description: USB PCIE wrapper pipe clock source - if: properties: @@ -63,7 +61,15 @@ allOf: properties: clocks: minItems: 7 - maxItems: 7 + items: + - description: Board XO clock source + - description: Sleep clock source + - description: PCIE 2lane PHY pipe clock source + - description: PCIE 2lane x1 PHY pipe clock source (For second lane) + - description: PCIE 2-lane PHY2 pipe clock source + - description: PCIE 2-lane PHY3 pipe clock source + - description: USB PCIE wrapper pipe clock source + - description: 375 MHz PPE clock generated from the CMN PLL unevaluatedProperties: false -- 2.34.1