From: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
To: Bjorn Andersson <andersson@kernel.org>,
Stephen Boyd <sboyd@kernel.org>,
Brian Masney <bmasney+clk@redhat.com>,
Jerome Brunet <jbrunet+clk@baylibre.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Georgi Djakov <djakov@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Varadarajan Narayanan <quic_varada@quicinc.com>,
Dmitry Baryshkov <lumag@kernel.org>,
Abel Vesa <abelvesa@kernel.org>,
Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>,
Sricharan Ramabadhran <quic_srichara@quicinc.com>,
Kathiravan T <quic_kathirav@quicinc.com>
Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-pm@vger.kernel.org,
Kathiravan Thirumoorthy
<kathiravan.thirumoorthy@oss.qualcomm.com>,
Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Subject: [PATCH 09/11] arm64: dts: qcom: ipq5424: Wire up PPE clock to GCC
Date: Mon, 21 Sep 2026 11:49:42 +0530 [thread overview]
Message-ID: <20260921-ipq_clk_changes-v1-9-d242e3d49648@oss.qualcomm.com> (raw)
In-Reply-To: <20260921-ipq_clk_changes-v1-0-d242e3d49648@oss.qualcomm.com>
Add the PPE 375 MHz clock generated by the CMN PLL to the GCC clock
controller inputs. GCC uses this clock as the source for the NSS
MEMNOC clocks.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/ipq5424.dtsi | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
index 95e2508ac145..64a06d615d61 100644
--- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
@@ -486,7 +486,8 @@ gcc: clock-controller@1800000 {
<&pcie1_phy>,
<&pcie2_phy>,
<&pcie3_phy>,
- <&ssphy_0>;
+ <&ssphy_0>,
+ <&cmn_pll IPQ5424_PPE_375MHZ_CLK>;
#clock-cells = <1>;
#reset-cells = <1>;
#interconnect-cells = <1>;
--
2.34.1
next prev parent reply other threads:[~2026-09-21 6:20 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-21 6:19 [PATCH 00/11] Add a few minor enhancements to the Qualcomm IPQ GCC drivers Kathiravan Thirumoorthy
2026-09-21 6:19 ` [PATCH 01/11] clk: qcom: ipq5018: add 24MHz rate for USB UTMI clock Kathiravan Thirumoorthy
2026-09-21 12:03 ` Abel Vesa
2026-09-21 6:19 ` [PATCH 02/11] clk: qcom: ipq5332: " Kathiravan Thirumoorthy
2026-09-21 12:03 ` Abel Vesa
2026-09-21 6:19 ` [PATCH 03/11] clk: qcom: ipq5210: " Kathiravan Thirumoorthy
2026-09-21 12:03 ` Abel Vesa
2026-09-21 6:19 ` [PATCH 04/11] arm64: dts: qcom: ipq9574: Wire up USB3 PHY PIPE clock to GCC Kathiravan Thirumoorthy
2026-09-21 11:55 ` Abel Vesa
2026-09-21 6:19 ` [PATCH 05/11] dt-bindings: clock: qcom: ipq5332-gcc: Describe clock inputs per compatible Kathiravan Thirumoorthy
2026-09-23 8:47 ` Krzysztof Kozlowski
2026-09-24 9:15 ` Kathiravan Thirumoorthy
2026-09-24 10:58 ` Krzysztof Kozlowski
2026-09-25 6:39 ` Kathiravan Thirumoorthy
2026-09-21 6:19 ` [PATCH 06/11] arm64: dts: qcom: ipq5424: Wire up USB3 PHY PIPE clock to GCC Kathiravan Thirumoorthy
2026-09-21 12:04 ` Abel Vesa
2026-09-21 6:19 ` [PATCH 07/11] dt-bindings: qcom,ipq5424: add NSS MEMNOC clock and ICC IDs Kathiravan Thirumoorthy
2026-09-22 12:33 ` Georgi Djakov
2026-09-21 6:19 ` [PATCH 08/11] clk: qcom: gcc-ipq5424: add the MEMNOC clocks needed for the NSS block Kathiravan Thirumoorthy
2026-09-21 12:05 ` Abel Vesa
2026-09-21 6:19 ` Kathiravan Thirumoorthy [this message]
2026-09-21 12:06 ` [PATCH 09/11] arm64: dts: qcom: ipq5424: Wire up PPE clock to GCC Abel Vesa
2026-09-21 6:19 ` [PATCH 10/11] clk: qcom: gcc-ipq5210: add UNIPHY XPCS reset entries Kathiravan Thirumoorthy
2026-09-21 12:06 ` Abel Vesa
2026-09-21 6:19 ` [PATCH 11/11] clk: qcom: apss-ipq5424: fix 'ipa' typos Kathiravan Thirumoorthy
2026-09-21 12:07 ` Abel Vesa
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