From: Ali Rouhi <arouhi@sitime.com>
To: "ivecera@redhat.com" <ivecera@redhat.com>
Cc: "jiri@resnulli.us" <jiri@resnulli.us>,
"vadim.fedorenko@linux.dev" <vadim.fedorenko@linux.dev>,
"arkadiusz.kubalewski@intel.com" <arkadiusz.kubalewski@intel.com>,
"robh@kernel.org" <robh@kernel.org>,
"krzk+dt@kernel.org" <krzk+dt@kernel.org>,
"conor+dt@kernel.org" <conor+dt@kernel.org>,
"cjubran@nvidia.com" <cjubran@nvidia.com>,
"pabeni@redhat.com" <pabeni@redhat.com>,
"Oleg.Zadorozhnyi@devoxsoftware.com"
<Oleg.Zadorozhnyi@devoxsoftware.com>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"netdev@vger.kernel.org" <netdev@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH net-next v9 10/15] dpll: sit9531x: add support to adjust output phase
Date: Mon, 21 Sep 2026 20:49:21 +0000 [thread overview]
Message-ID: <20260921204918.53170-3-arouhi@sitime.com> (raw)
In-Reply-To: <bde28182-fab2-4ae1-b5f8-d425c2d0aeee@redhat.com>
On 9/17/26 11:55 AM, Ivan Vecera wrote:
>> + if (phase_ps == 0) {
>> + abs_ps = 0;
>> + } else if (phase_ps > 0) {
>> + abs_ps = (u64)phase_ps;
>> + div64_u64_rem(abs_ps, t_out_ps, &abs_ps);
>> + phase_norm_ps = abs_ps;
>> + } else {
>> + u64 advance = (u64)(-(s64)phase_ps);
>> +
>> + div64_u64_rem(advance, t_out_ps, &advance);
>> + phase_norm_ps = -(s64)advance;
>> + abs_ps = (advance == 0) ? 0 : (t_out_ps - advance);
>> + }
>
> This if-else branches could be reduced to:
> <snip>
> abs_ps = abs(phase_ps); /* Safe. INT_MIN is not possible here*/
> div64_u64_rem(abs_ps, t_out_ps, &abs_ps);
> phase_norm_ps = phase_ps < 0 ? -(s64)abs_ps : (s64)abs_ps;
> abs_ps = phase_ps < 0 && abs_ps ? t_out_ps - abs_ps : abs_ps;
> </snip>
Taken as written. v10 has those four lines in place of the three-way
branch, with only a pair of parentheses added on the last one.
Your INT_MIN note holds, and for a reason I wanted to confirm rather
than take on trust: the core rejects a phase-adjust request outside the
advertised phase range before the driver is called, and that range is
+/-1 ms expressed in ps. The value that reaches this function is
therefore bounded well inside s32, and abs() cannot be handed INT_MIN.
The comment above the block now says so, so the next reader does not
have to re-derive it.
>> + coarse = mul_u64_u64_div_u64(abs_ps, fvco, 1000000000000ULL);
>> + if (coarse >= (1ULL << SIT9531X_OUT_PRG_COARSE_BITS))
>> + return -ERANGE;
>> +
>> + /* Fine delay = round((abs_ps - coarse * vco_period_ps) / 30 ps) */
>> + coarse_ps = mul_u64_u64_div_u64(coarse, 1000000000000ULL, fvco);
>> + rem_ps = (abs_ps > coarse_ps) ? (abs_ps - coarse_ps) : 0;
>> + if (rem_ps) {
>> + u64 steps;
>> +
>> + steps = div64_u64(rem_ps + SIT9531X_OUT_PRG_FINE_STEP_PS / 2,
>> + SIT9531X_OUT_PRG_FINE_STEP_PS);
>> + if (steps > SIT9531X_OUT_PRG_FINE_MAX)
>> + steps = SIT9531X_OUT_PRG_FINE_MAX;
>> + fine = (u8)steps;
>> + }
>
> Also this whole block can be skipped (and set coarse to 0) in case of
> abs_ps == 0 to avoid expensive divisions.
Also taken. The coarse and fine encoding now sits inside an
if (abs_ps) block, and coarse is initialized to 0 at its declaration,
so a zero offset does no division at all. rem_ps moved inside the block
with it, since nothing outside needs it.
Patch 10 in v10 carries
Suggested-by: Ivan Vecera <ivecera@redhat.com>
v10 is posted:
https://lore.kernel.org/netdev/20260921201108.42676-1-arouhi@sitime.com/
Thanks,
Ali
next prev parent reply other threads:[~2026-09-21 20:49 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-15 0:00 [PATCH net-next v9 00/15] dpll: add SiTime SiT9531x DPLL clock driver Ali Rouhi
2026-09-15 0:00 ` [PATCH net-next v9 01/15] dt-bindings: vendor-prefixes: add SiTime Corporation Ali Rouhi
2026-09-15 0:00 ` [PATCH net-next v9 02/15] dt-bindings: dpll: add SiTime SiT95316 clock generator Ali Rouhi
2026-09-17 15:01 ` netdev-bot+sashiko
2026-09-15 0:00 ` [PATCH net-next v9 03/15] dpll: add basic SiTime SiT9531x support Ali Rouhi
2026-09-17 8:42 ` Ivan Vecera
2026-09-21 20:49 ` Ali Rouhi
2026-09-17 15:01 ` netdev-bot+sashiko
2026-09-15 0:00 ` [PATCH net-next v9 05/15] dpll: sit9531x: register DPLL devices and pins Ali Rouhi
2026-09-17 15:01 ` netdev-bot+sashiko
2026-09-15 0:00 ` [PATCH net-next v9 04/15] dpll: sit9531x: read DPLL types and pin properties from system firmware Ali Rouhi
2026-09-17 9:42 ` Ivan Vecera
2026-09-21 20:49 ` Ali Rouhi
2026-09-17 15:01 ` netdev-bot+sashiko
2026-09-15 0:00 ` [PATCH net-next v9 06/15] dpll: sit9531x: implement input pin state on a DPLL Ali Rouhi
2026-09-17 15:01 ` netdev-bot+sashiko
2026-09-15 0:00 ` [PATCH net-next v9 08/15] dpll: sit9531x: add support to get and set frequency on pins Ali Rouhi
2026-09-17 15:01 ` netdev-bot+sashiko
2026-09-15 0:00 ` [PATCH net-next v9 07/15] dpll: sit9531x: add support to get and set priority on input pins Ali Rouhi
2026-09-17 15:01 ` netdev-bot+sashiko
2026-09-15 0:00 ` [PATCH net-next v9 09/15] dpll: sit9531x: implement output pin state on a DPLL Ali Rouhi
2026-09-17 15:01 ` netdev-bot+sashiko
2026-09-15 0:00 ` [PATCH net-next v9 10/15] dpll: sit9531x: add support to adjust output phase Ali Rouhi
2026-09-17 9:55 ` Ivan Vecera
2026-09-21 20:49 ` Ali Rouhi [this message]
2026-09-17 15:01 ` netdev-bot+sashiko
2026-09-15 0:00 ` [PATCH net-next v9 11/15] dpll: sit9531x: add support to get and set esync on pins Ali Rouhi
2026-09-17 15:01 ` netdev-bot+sashiko
2026-09-15 0:00 ` [PATCH net-next v9 12/15] dpll: sit9531x: add support to get phase offset on the connected input pin Ali Rouhi
2026-09-17 15:01 ` netdev-bot+sashiko
2026-09-15 0:00 ` [PATCH net-next v9 14/15] dpll: sit9531x: model the inter-PLL sync net as a pair of pins Ali Rouhi
2026-09-17 15:01 ` netdev-bot+sashiko
2026-09-15 0:00 ` [PATCH net-next v9 13/15] dpll: sit9531x: add support to get fractional frequency offset Ali Rouhi
2026-09-17 15:01 ` netdev-bot+sashiko
2026-09-15 0:00 ` [PATCH net-next v9 15/15] dpll: sit9531x: allow the device tree to override two board facts Ali Rouhi
2026-09-17 15:02 ` netdev-bot+sashiko
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