From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C4FBF3911AF; Tue, 22 Sep 2026 14:46:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790088404; cv=none; b=sZnmXX+uBWlsBxAjpj4tsYcuz3kG+OSlzYbNNBELqNbIS7fbTYW9G5udv7rn8kF8d03xdlG6Zra9YOEZxIiBJsftuDKzeUxNhFnD+Vs0aXnZxJKZOVMgtDz2m9d+v9DmJVw4KWA38zBHMEewXxkiA6aQhkpgwjp1JUwNNGro4LM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790088404; c=relaxed/simple; bh=1kZch10bGj8PCCnDosR7xVAAGOeC5xf//7Byt2ewcz4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=tnngWGn5xM0UyUsdAnGG6Xd6x3pncWsU+bzW7mEYdzUj/RpGq6IcB4rxlsn+vJM7MxXd51CTA/DfUITnzsa1jkI+XoNKxQiKRv/guztsi6ZR9vMWXmuXj9X5hrZq92h0xMJEqYA/dl+auCqWfJEf5pQK6MlW2PBPM5NLA2L7y2M= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=cgZ2qpZc; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="cgZ2qpZc" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 871BC1F00899; Tue, 22 Sep 2026 14:46:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1790088402; bh=MlpgsnaDiTpidihd3mBcz2ZDd8K8o0293XNhbkNgmmM=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=cgZ2qpZcINv5q5/oUFQR2RZdb3XRIVfCbt8mOHnssVxzKyKhbuVjO7AyusulY4nMw A42PJ2VP4PE2sUkuz5WpEm/DxKYtTw8L07HJLp5xai1ngV3grxKIY3KxF+8Bgs2r0j 65S0d2e6zIIk/cuC5oOD29lPcwBQnjp9QvO8FZ2WzgpKD2s1rV/2l69yCDA+byHPVG sdtTh/Qwh9+gtqc6EREYVH4qMHigIv9cECa5jbEFJdkHl2jnfTuZqFETZK5jw1ekNz ujG07RCIzEAVXNINbJL7nHbP5TcsURKD/Y8w7P5gkp0zq1gPGxjkWig1uDIHmBichH yATv0LWPFJAnw== From: Claudiu Beznea To: lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, robh@kernel.org, bhelgaas@google.com, p.zabel@pengutronix.de Cc: claudiu.beznea@tuxon.dev, linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Claudiu Beznea , stable@vger.kernel.org Subject: [PATCH v4 1/8] PCI: rzg3s-host: Follow hardware manual clock/reset initialization order Date: Tue, 22 Sep 2026 17:46:21 +0300 Message-ID: <20260922144629.586997-2-claudiu.beznea@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260922144629.586997-1-claudiu.beznea@kernel.org> References: <20260922144629.586997-1-claudiu.beznea@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Claudiu Beznea The RZ/G3S PCIe hardware manual specifies that the clocks must be enabled before the reset signals are deasserted during initialization. Follow this sequence in the probe(), suspend(), and resume() paths to match the hardware requirements and avoid potential issues. Fixes: 7ef502fb35b2 ("PCI: Add Renesas RZ/G3S host controller driver") Cc: stable@vger.kernel.org Signed-off-by: Claudiu Beznea --- Changes in v4: - none Changes in v3: - none, this patch is new drivers/pci/controller/pcie-rzg3s-host.c | 40 +++++++++++++----------- 1 file changed, 21 insertions(+), 19 deletions(-) diff --git a/drivers/pci/controller/pcie-rzg3s-host.c b/drivers/pci/controller/pcie-rzg3s-host.c index 077cfb0834b3..e1105b1f2652 100644 --- a/drivers/pci/controller/pcie-rzg3s-host.c +++ b/drivers/pci/controller/pcie-rzg3s-host.c @@ -1888,10 +1888,6 @@ static int rzg3s_pcie_probe(struct platform_device *pdev) if (ret) goto sysc_signal_restore; - ret = rzg3s_pcie_power_resets_deassert(host); - if (ret) - goto sysc_signal_restore; - pm_runtime_enable(dev); /* @@ -1902,12 +1898,16 @@ static int rzg3s_pcie_probe(struct platform_device *pdev) if (ret) goto rpm_disable; + ret = rzg3s_pcie_power_resets_deassert(host); + if (ret) + goto rpm_put; + raw_spin_lock_init(&host->hw_lock); ret = rzg3s_pcie_host_setup(host, rzg3s_pcie_init_irqdomain, rzg3s_pcie_teardown_irqdomain); if (ret) - goto rpm_put; + goto power_resets_assert; bridge->sysdata = host; bridge->ops = &rzg3s_pcie_root_ops; @@ -1922,12 +1922,13 @@ static int rzg3s_pcie_probe(struct platform_device *pdev) clk_disable_unprepare(host->port.refclk); rzg3s_pcie_teardown_irqdomain(host); host->data->config_deinit(host); +power_resets_assert: + reset_control_bulk_assert(host->data->num_power_resets, + host->power_resets); rpm_put: pm_runtime_put_sync(dev); rpm_disable: pm_runtime_disable(dev); - reset_control_bulk_assert(host->data->num_power_resets, - host->power_resets); sysc_signal_restore: /* * SYSC RST_RSM_B signal need to be asserted before turning off the @@ -1948,10 +1949,6 @@ static int rzg3s_pcie_suspend_noirq(struct device *dev) struct rzg3s_sysc *sysc = host->sysc; int ret; - ret = pm_runtime_put_sync(dev); - if (ret) - return ret; - clk_disable_unprepare(port->refclk); /* SoC-specific de-initialization */ @@ -1964,13 +1961,19 @@ static int rzg3s_pcie_suspend_noirq(struct device *dev) if (ret) goto config_reinit; - ret = rzg3s_sysc_config_func(sysc, RZG3S_SYSC_FUNC_ID_RST_RSM_B, 0); + ret = pm_runtime_put_sync(dev); if (ret) goto power_resets_restore; + ret = rzg3s_sysc_config_func(sysc, RZG3S_SYSC_FUNC_ID_RST_RSM_B, 0); + if (ret) + goto rpm_resume; + return 0; /* Restore the previous state if any error happens */ +rpm_resume: + pm_runtime_resume_and_get(dev); power_resets_restore: reset_control_bulk_deassert(data->num_power_resets, host->power_resets); @@ -1980,7 +1983,6 @@ static int rzg3s_pcie_suspend_noirq(struct device *dev) data->config_post_init(host); refclk_restore: clk_prepare_enable(port->refclk); - pm_runtime_resume_and_get(dev); return ret; } @@ -2009,18 +2011,18 @@ static int rzg3s_pcie_resume_noirq(struct device *dev) goto assert_rst_rsm_b; } - ret = rzg3s_pcie_power_resets_deassert(host); + ret = pm_runtime_resume_and_get(dev); if (ret) goto assert_rst_rsm_b; - ret = pm_runtime_resume_and_get(dev); + ret = rzg3s_pcie_power_resets_deassert(host); if (ret) - goto assert_power_resets; + goto rpm_put; ret = rzg3s_pcie_host_setup(host, rzg3s_pcie_msi_hw_setup, rzg3s_pcie_msi_hw_teardown); if (ret) - goto rpm_put; + goto assert_power_resets; return 0; @@ -2028,11 +2030,11 @@ static int rzg3s_pcie_resume_noirq(struct device *dev) * If any error happens there is no way to recover the IP. Put it in the * lowest possible power state. */ -rpm_put: - pm_runtime_put_sync(dev); assert_power_resets: reset_control_bulk_assert(data->num_power_resets, host->power_resets); +rpm_put: + pm_runtime_put_sync(dev); assert_rst_rsm_b: rzg3s_sysc_config_func(sysc, RZG3S_SYSC_FUNC_ID_RST_RSM_B, 0); return ret; -- 2.43.0