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[46.193.35.178]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4886876c500sm374681f8f.19.2026.09.22.11.44.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Sep 2026 11:44:56 -0700 (PDT) From: Srinivas Kandagatla To: Bjorn Andersson , Stephen Boyd , Krzysztof Kozlowski , Rob Herring , Conor Dooley Cc: Abel Vesa , Brian Masney , Jerome Brunet , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Srinivas Kandagatla Subject: [PATCH 0/4] clk: qcom: Add LPASS clock/reset controllers for Glymur Date: Tue, 22 Sep 2026 19:44:21 +0100 Message-ID: <20260922184425.56114-1-srinivas.kandagatla@oss.qualcomm.com> X-Mailer: git-send-email 2.53.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: FXhyEleomAVPJEoyUhyuEP_B4bnV2xrM X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTIyMDI3NSBTYWx0ZWRfX2qvm5/A6me6i AGq162XHKgAQp1pDVryd9dCFqIfc6mbGd6yfa7RaT3wKHlNI7WuZnGb+KL3qtICANgtDHBc80S4 MxxMiDs4NR3OYxi0p6xtC6Xbl8AWNU5Uzt+9frc39aRc5zhx0jYZcWQb7pdxP912Yue/es+e4jX u78JqC1O9jK9I+PeEqsD6DTCZtQ9Tmz4P6EmN2Q+9GJmzTy9XM9xNy2im9gcXkXRg6mWYfdjpmO 7Z1OzVty2yRvElFKuYrKJuUIM57CsLeS8aRWTkZnyeVFWD+gI51pVu/Al+hRl4OFdnXdNxF/FLq EUGKZewF+4aas1wVP2Fxy7DP48oTiugywbSbC8fPUFM12K7KrVfAG7TDzElgt3rl+C2CPrMVv5f wv8Zx4wpvEuvP6y3ecdN8eBEpp7LTYXKHCkY6Gzaa/NYTP9h00rodLwFJavoVCPYZ1RaR7grpAi htGaVm5O5pl8hV5ivBQ== X-Proofpoint-Spam-Info: AW1haW4tMjYwOTIyMDI3NSBTYWx0ZWRfX5w0ZJOG2fe/A 97wPPddhIXLSTu8+2bywuUzjYnw3O6kxW1IAKU+K06+SWdOi3x9NoMjEPozEigVu//2DEjtLg58 dwMGNSHyICBqJnbj/E5sRQOXABNWURg= X-Authority-Analysis: v=2.4 cv=SuAFe/O0 c=1 sm=1 tr=0 ts=6ab2ccaa cx=c_pps a=JIY1xp/sjQ9K5JH4t62bdg==:117 a=Hji71o54RgNgZYqDgtlrhw==:17 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=68KCznAa1mAgJHz0fDQA:9 a=tNoRWFLymzeba-QzToBc:22 X-Proofpoint-ORIG-GUID: FXhyEleomAVPJEoyUhyuEP_B4bnV2xrM X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-22_03,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 clxscore=1015 suspectscore=0 spamscore=0 phishscore=0 malwarescore=0 priorityscore=1501 adultscore=0 impostorscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609220275 Add DT bindings and clock-controller drivers for the two LPASS reset providers on the Glymur SoC: - qcom,glymur-lpassaudiocc (LPASS Audio CC CSR): RX + WSA1..WSA4 SoundWire CGCR resets - qcom,glymur-lpasscc (LPASS CC CSR): TX SoundWire CGCR reset Only resets are exposed for now; the Q6DSP owns LPASS clocks via the Q6PRM service on the GPR rpmsg channel, matching the existing SC8280XP pattern (commits a5c9c3ba243a, c2ef1ec97c1f). The reset providers are required by the LPASS audio macros and the SoundWire controller to come out of reset on Glymur. Srinivas Kandagatla (4): dt-bindings: clock: Add LPASS AUDIOCC and reset controller for Glymur dt-bindings: clock: Add LPASSCC and reset controller for Glymur clk: qcom: Add lpass audio clock controller driver for Glymur clk: qcom: Add lpass clock controller driver for Glymur .../bindings/clock/qcom,glymur-lpasscc.yaml | 60 ++++++++++++ drivers/clk/qcom/Kconfig | 11 +++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/lpasscc-glymur.c | 91 +++++++++++++++++++ .../dt-bindings/clock/qcom,glymur-lpasscc.h | 19 ++++ 5 files changed, 182 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,glymur-lpasscc.yaml create mode 100644 drivers/clk/qcom/lpasscc-glymur.c create mode 100644 include/dt-bindings/clock/qcom,glymur-lpasscc.h -- 2.53.0