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[46.193.35.178]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4886876c500sm374681f8f.19.2026.09.22.11.44.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Sep 2026 11:44:57 -0700 (PDT) From: Srinivas Kandagatla To: Bjorn Andersson , Stephen Boyd , Krzysztof Kozlowski , Rob Herring , Conor Dooley Cc: Abel Vesa , Brian Masney , Jerome Brunet , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Srinivas Kandagatla Subject: [PATCH 1/4] dt-bindings: clock: Add LPASS AUDIOCC and reset controller for Glymur Date: Tue, 22 Sep 2026 19:44:22 +0100 Message-ID: <20260922184425.56114-2-srinivas.kandagatla@oss.qualcomm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260922184425.56114-1-srinivas.kandagatla@oss.qualcomm.com> References: <20260922184425.56114-1-srinivas.kandagatla@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: gX8CvGP_-FQWxtXP53FovtHDmk8XIl-- X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTIyMDI3NSBTYWx0ZWRfXyqbtklTBgT2W J9zhv2w1d6k+LB+Xbe0eCc4clKcUP5KdQgzQhr7n6rDbqvLagWcxHH765ttNRX1Y0L0kJAVkny+ UwMEDSlUZ4ymaeIml3K1ObWLy3srtsEBpjHdX3RZ5rhclBcSAFInJf5X/zDIfY6JoKcCsnCS7E1 d8RraWHWlqTcIGK+9pOIJZELG8IuvoxZaokeoB+PcmUn2USH0IhDr+NDC5Rc4TGf0DlzXOt8Tei oaVo30YhLr4YdzuK2gRce19mP5XeAxpwPmw1EKaSfdJdn25Q73UCii77lmxAgm2SxQYajmkG+s7 FS68A8GPkA23qzPmzjoFi96J6Hc6IKllsibEF1kRYKUMEu7a+JZ2VK1WVCTXc6k4q+qU03OTZ7F h0DaGuVp95pu4iwpm3zv5MV92434XcE8iAHKX8YUWtn6AbcHxiNzFgXHw8I9q2ZmPL5tk/EQNCo ZXrPo/F42Ht/t7ekRqA== X-Proofpoint-Spam-Info: AW1haW4tMjYwOTIyMDI3NSBTYWx0ZWRfX+1LdpyjB2I+M JA51WygcBigFR04DaVybqRRt6RauFHHZJ7VLM/NroFTZ8PyzVxPWdcbE7837lygzyvBhQVbvbMp Yh7VQchlp12W7Jx/OEho3wXigxLJdWs= X-Authority-Analysis: v=2.4 cv=SuAFe/O0 c=1 sm=1 tr=0 ts=6ab2ccab cx=c_pps a=UbhLPJ621ZpgOD2l3yZY1w==:117 a=Hji71o54RgNgZYqDgtlrhw==:17 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=yiKMOllxs-7wBVDooBUA:9 a=TOPH6uDL9cOC6tEoww4z:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-ORIG-GUID: gX8CvGP_-FQWxtXP53FovtHDmk8XIl-- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-22_03,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 clxscore=1015 suspectscore=0 spamscore=0 phishscore=0 malwarescore=0 priorityscore=1501 adultscore=0 impostorscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609220275 The LPASS (Low Power Audio Subsystem) Audio clock controller provides reset support when it is under the control of Q6DSP. Add support for those resets and adds IDs for clients to request the reset. Signed-off-by: Srinivas Kandagatla --- .../bindings/clock/qcom,glymur-lpasscc.yaml | 50 +++++++++++++++++++ .../dt-bindings/clock/qcom,glymur-lpasscc.h | 16 ++++++ 2 files changed, 66 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,glymur-lpasscc.yaml create mode 100644 include/dt-bindings/clock/qcom,glymur-lpasscc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,glymur-lpasscc.yaml b/Documentation/devicetree/bindings/clock/qcom,glymur-lpasscc.yaml new file mode 100644 index 000000000000..c047c0174a93 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,glymur-lpasscc.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,glymur-lpasscc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm LPASS Core & Audio Clock Controller on Glymur + +maintainers: + - Srinivas Kandagatla + +description: | + Qualcomm LPASS core and audio clock control module provides the clocks, + and reset on Glymur. + + See also: + include/dt-bindings/clock/qcom,glymur-lpasscc.h + +properties: + compatible: + enum: + - qcom,glymur-lpassaudiocc + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + #include + lpass_audiocc: clock-controller@32a9000 { + compatible = "qcom,glymur-lpassaudiocc"; + reg = <0x032a9000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,glymur-lpasscc.h b/include/dt-bindings/clock/qcom,glymur-lpasscc.h new file mode 100644 index 000000000000..3006b12e385e --- /dev/null +++ b/include/dt-bindings/clock/qcom,glymur-lpasscc.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_LPASSCC_GLYMUR_H +#define _DT_BINDINGS_CLK_QCOM_LPASSCC_GLYMUR_H + +/* LPASS AUDIO CC CSR */ +#define LPASS_AUDIO_SWR_RX_CGCR 0 +#define LPASS_AUDIO_SWR_WSA1_CGCR 1 +#define LPASS_AUDIO_SWR_WSA2_CGCR 2 +#define LPASS_AUDIO_SWR_WSA3_CGCR 3 +#define LPASS_AUDIO_SWR_WSA4_CGCR 4 + +#endif -- 2.53.0