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[46.193.35.178]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4886876c500sm374681f8f.19.2026.09.22.11.44.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Sep 2026 11:45:00 -0700 (PDT) From: Srinivas Kandagatla To: Bjorn Andersson , Stephen Boyd , Krzysztof Kozlowski , Rob Herring , Conor Dooley Cc: Abel Vesa , Brian Masney , Jerome Brunet , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Srinivas Kandagatla Subject: [PATCH 3/4] clk: qcom: Add lpass audio clock controller driver for Glymur Date: Tue, 22 Sep 2026 19:44:24 +0100 Message-ID: <20260922184425.56114-4-srinivas.kandagatla@oss.qualcomm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260922184425.56114-1-srinivas.kandagatla@oss.qualcomm.com> References: <20260922184425.56114-1-srinivas.kandagatla@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: 8k-qyrsj6uvIhMvBg28gea0rgwAFqVk8 X-Proofpoint-Spam-Info: AW1haW4tMjYwOTIyMDI3NSBTYWx0ZWRfX0kTCyMEKXvjU mGaXxKer3OPC398OmLN7PYvlxl0pWeULjxuAv0jz/v9ZnBzBJo7kAKecWMHGseudRqYEJgMbrCM 1I2u7I0NLyDknA0M7FZivf245uo9Fnc= X-Proofpoint-ORIG-GUID: 8k-qyrsj6uvIhMvBg28gea0rgwAFqVk8 X-Authority-Analysis: v=2.4 cv=atQnmiZV c=1 sm=1 tr=0 ts=6ab2ccae cx=c_pps a=JIY1xp/sjQ9K5JH4t62bdg==:117 a=Hji71o54RgNgZYqDgtlrhw==:17 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=7GdS1con5BCYmhUutoQA:9 a=tNoRWFLymzeba-QzToBc:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTIyMDI3NSBTYWx0ZWRfX8JxaqhWbg+j+ NJSayAEft5OqfvKA+oURfU2I3WAXQkaXbNskvA/rip1UVSjQzq58R7UdtptJLssc25jctO9KfBO 0DslEn5KOxO16g0VLX2BV05y4BLp3BetKhK1JT2XL/A3E6i5e0T9rEFhIO36ktV+al8ueAchFO4 vg1VGNZRKHaDA0/AsxAmM7p2CfZcVZgOPRncdkn/j1yJY8XRa6hk54D+b/kSpn4I8IsupBHZJwT 7SjPdFKzTCzlKo94pynXamhorNCqhLDf5bVw5MS2lkq0Ji4qUTy0WfCl+n8dD01YXKqOk4oUqXF 47TOq0e9LMcpzoJw4BfuWTgesZBBVgDSo510qGANoPqco4x1MCq3Bwbop65O5Yz/RBBPeP2L2GO wLvL1Z6iQgJ2/Ryzly1BBckcpnMxDLCkSr275/vwMRo/0Kei0AwZ/kSCIRKTjbyLAgUW6q4576S 7vUI5Y7czgqXBBlmx/A== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-22_03,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 phishscore=0 lowpriorityscore=0 spamscore=0 malwarescore=0 clxscore=1015 priorityscore=1501 adultscore=0 bulkscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609220275 Add support for the lpass audio clock controller found on Glymur based devices. This would allow lpass peripheral loader drivers to control the clocks and bring the subsystems out of reset. Currently this patch only supports resets as the Q6DSP is in control of LPASS IP which manages most of the clocks via Q6PRM service on GPR rpmsg channel. Signed-off-by: Srinivas Kandagatla --- drivers/clk/qcom/Kconfig | 11 +++++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/lpasscc-glymur.c | 70 +++++++++++++++++++++++++++++++ 3 files changed, 82 insertions(+) create mode 100644 drivers/clk/qcom/lpasscc-glymur.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index b3ffe1dced01..1e571c237fc1 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -1253,6 +1253,17 @@ config SC_LPASSCC_8280XP Say Y if you want to use the LPASS branch clocks of the LPASS clock controller to reset the LPASS subsystem. +config SC_LPASSCC_GLYMUR + tristate "GLYMUR Low Power Audio Subsystem (LPASS) Clock Controller" + depends on ARM64 || COMPILE_TEST + default m if ARCH_QCOM + help + Support for the LPASS clock controller on Glymur devices. + Say Y if you want to use the LPASS branch clocks of the LPASS clock + controller to reset the LPASS subsystem. Required for the LPASS + audio macros and the SoundWire compute-mode controller to leave + reset on Glymur. + config SC_LPASS_CORECC_7180 tristate "SC7180 LPASS Core Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index a6c676f68b79..c8348218b6b8 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -149,6 +149,7 @@ obj-$(CONFIG_SC_LPASSCC_7280) += lpasscc-sc7280.o obj-$(CONFIG_SC_LPASSCC_8280XP) += lpasscc-sc8280xp.o obj-$(CONFIG_SC_LPASS_CORECC_7180) += lpasscorecc-sc7180.o obj-$(CONFIG_SC_LPASS_CORECC_7280) += lpasscorecc-sc7280.o lpassaudiocc-sc7280.o +obj-$(CONFIG_SC_LPASSCC_GLYMUR) += lpasscc-glymur.o obj-$(CONFIG_SC_VIDEOCC_7180) += videocc-sc7180.o obj-$(CONFIG_SC_VIDEOCC_7280) += videocc-sc7280.o obj-$(CONFIG_SDM_CAMCC_845) += camcc-sdm845.o diff --git a/drivers/clk/qcom/lpasscc-glymur.c b/drivers/clk/qcom/lpasscc-glymur.c new file mode 100644 index 000000000000..97fc099983b6 --- /dev/null +++ b/drivers/clk/qcom/lpasscc-glymur.c @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "common.h" +#include "reset.h" + +static const struct qcom_reset_map lpass_audiocc_glymur_resets[] = { + [LPASS_AUDIO_SWR_RX_CGCR] = { 0xA0, 1 }, + [LPASS_AUDIO_SWR_WSA1_CGCR] = { 0xB0, 1 }, + [LPASS_AUDIO_SWR_WSA2_CGCR] = { 0xD8, 1 }, + [LPASS_AUDIO_SWR_WSA3_CGCR] = { 0x300C, 1 }, + [LPASS_AUDIO_SWR_WSA4_CGCR] = { 0x301C, 1 }, +}; + +static const struct regmap_config lpass_audiocc_glymur_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .name = "lpass-audio-csr", + .max_register = 0x1000, +}; + +static const struct qcom_cc_desc lpass_audiocc_glymur_reset_desc = { + .config = &lpass_audiocc_glymur_regmap_config, + .resets = lpass_audiocc_glymur_resets, + .num_resets = ARRAY_SIZE(lpass_audiocc_glymur_resets), +}; + +static const struct of_device_id lpasscc_glymur_match_table[] = { + { + .compatible = "qcom,glymur-lpassaudiocc", + .data = &lpass_audiocc_glymur_reset_desc, + }, + { } +}; +MODULE_DEVICE_TABLE(of, lpasscc_glymur_match_table); + +static int lpasscc_glymur_probe(struct platform_device *pdev) +{ + const struct qcom_cc_desc *desc = of_device_get_match_data(&pdev->dev); + + return qcom_cc_probe_by_index(pdev, 0, desc); +} + +static struct platform_driver lpasscc_glymur_driver = { + .probe = lpasscc_glymur_probe, + .driver = { + .name = "lpasscc-glymur", + .of_match_table = lpasscc_glymur_match_table, + }, +}; + +module_platform_driver(lpasscc_glymur_driver); + +MODULE_AUTHOR("Srinivas Kandagatla "); +MODULE_DESCRIPTION("QTI LPASSCC Glymur Driver"); +MODULE_LICENSE("GPL"); -- 2.53.0