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Compared to the Iris4 generation, this block has - additional power domains for internal NoC(cx & mm). - additional clock for internal NoC(cx_iface). - additional power domain and clock for apv codec. - different reset lines. Signed-off-by: Wangao Wang --- .../devicetree/bindings/media/qcom,hawi-iris.yaml | 256 +++++++++++++++++++++ 1 file changed, 256 insertions(+) diff --git a/Documentation/devicetree/bindings/media/qcom,hawi-iris.yaml b/Documentation/devicetree/bindings/media/qcom,hawi-iris.yaml new file mode 100644 index 0000000000000000000000000000000000000000..13e346414a231af9a146076de6a3fa9e9c488624 --- /dev/null +++ b/Documentation/devicetree/bindings/media/qcom,hawi-iris.yaml @@ -0,0 +1,256 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/qcom,hawi-iris.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Hawi SoC Iris video encoder and decoder + +maintainers: + - Vikash Garodia + - Dikshita Agarwal + +description: + The Iris video processing unit on Qualcomm Hawi SoC is a video encode and + decode accelerator. + +properties: + compatible: + enum: + - qcom,hawi-iris + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 13 + + clock-names: + items: + - const: iface + - const: ifacec + - const: core + - const: core_freerun + - const: core_ctl_freerun + - const: core_debug + - const: cx_iface + - const: vcodec0_core + - const: vcodec_vpp0 + - const: vcodec_vpp1 + - const: vcodec_vpp0_vpp1_gating + - const: vcodec_apv + - const: vcodec_bse + + firmware-name: + maxItems: 1 + + interconnects: + maxItems: 2 + + interconnect-names: + items: + - const: cpu-cfg + - const: video-mem + + power-domains: + maxItems: 9 + + power-domain-names: + items: + - const: venus + - const: vcodec0 + - const: mxc + - const: mmcx + - const: vpp0 + - const: vpp1 + - const: apv + - const: mm-int + - const: cx-int + + resets: + maxItems: 2 + + reset-names: + items: + - const: bus0 + - const: core + + iommus: + maxItems: 4 + + dma-coherent: true + + operating-points-v2: true + + opp-table: + type: object + +required: + - compatible + - dma-coherent + - interconnects + - interconnect-names + - power-domain-names + - resets + - reset-names + +allOf: + - $ref: qcom,venus-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + #include + + video-codec@2000000 { + compatible = "qcom,hawi-iris"; + reg = <0x02000000 0xf0000>; + + interrupts = ; + + clocks = <&gcc GCC_VIDEO_AXI0_CLK>, + <&gcc GCC_VIDEO_AXI0C_CLK>, + <&videocc VIDEO_CC_MVS0C_CLK>, + <&videocc VIDEO_CC_MVS0C_FREERUN_CLK>, + <&videocc VIDEO_CC_MVS0C_CTL_FREERUN_CLK>, + <&videocc VIDEO_CC_MVS0C_DEBUG_CLK>, + <&videocc VIDEO_CC_CX_AXI0_CLK>, + <&videocc VIDEO_CC_MVS0_CLK>, + <&videocc VIDEO_CC_MVS0_VPP0_CLK>, + <&videocc VIDEO_CC_MVS0_VPP1_CLK>, + <&videocc VIDEO_CC_MVS0_VPP0_VPP1_GATING_CLK>, + <&videocc VIDEO_CC_MVS0A_CLK>, + <&videocc VIDEO_CC_MVS0B_CLK>; + clock-names = "iface", + "ifacec", + "core", + "core_freerun", + "core_ctl_freerun", + "core_debug", + "cx_iface", + "vcodec0_core", + "vcodec_vpp0", + "vcodec_vpp1", + "vcodec_vpp0_vpp1_gating", + "vcodec_apv", + "vcodec_bse"; + + dma-coherent; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_IRIS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_VIDEO_MVP QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "cpu-cfg", + "video-mem"; + + memory-region = <&video_mem>; + + power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>, + <&videocc VIDEO_CC_MVS0_GDSC>, + <&rpmhpd RPMHPD_MXC>, + <&rpmhpd RPMHPD_MMCX>, + <&videocc VIDEO_CC_MVS0_VPP0_GDSC>, + <&videocc VIDEO_CC_MVS0_VPP1_GDSC>, + <&videocc VIDEO_CC_MVS0A_GDSC>, + <&videocc VIDEO_CC_MM_INT_GDSC>, + <&videocc VIDEO_CC_AXI0_CX_INT_GDSC>; + power-domain-names = "venus", + "vcodec0", + "mxc", + "mmcx", + "vpp0", + "vpp1", + "apv", + "mm-int", + "cx-int"; + + resets = <&gcc GCC_VIDEO_AXI0C_CLK_ARES>, + <&videocc VIDEO_CC_MVS0C_CTL_FREERUN_CLK_ARES>; + reset-names = "bus0", + "core"; + + operating-points-v2 = <&iris_opp_table>; + + #address-cells = <1>; + #size-cells = <1>; + dma-ranges = <0x0 0x0 0xffc00000>; + + non-pixel { + iommus = <&apps_smmu 0x1540 0x0000>, + <&apps_smmu 0x1620 0x0000>, + <&apps_smmu 0x1544 0x0000>; + iommu-ranges = <0x32000000 0xcdc00000>; + }; + + pixel { + iommus = <&apps_smmu 0x1543 0x0000>; + }; + + iris_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-150000000 { + opp-hz = /bits/ 64 <150000000 150000000 150000000 225000000>; + required-opps = <&rpmhpd_opp_low_svs_d2>, + <&rpmhpd_opp_low_svs_d2>; + }; + + opp-285000000 { + opp-hz = /bits/ 64 <285000000 240000000 240000000 360000000>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs_d0>; + }; + + opp-338000000 { + opp-hz = /bits/ 64 <338000000 338000000 338000000 507000000>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + }; + + opp-420000000 { + opp-hz = /bits/ 64 <420000000 420000000 420000000 630000000>; + required-opps = <&rpmhpd_opp_svs_l1>, + <&rpmhpd_opp_svs>; + }; + + opp-444000000 { + opp-hz = /bits/ 64 <444000000 444000000 444000000 666000000>; + required-opps = <&rpmhpd_opp_svs_l1>, + <&rpmhpd_opp_svs_l1>; + }; + + opp-560000000 { + opp-hz = /bits/ 64 <560000000 533000000 533000000 800000000>; + required-opps = <&rpmhpd_opp_svs_l1>, + <&rpmhpd_opp_nom>; + }; + + opp-630000000 { + opp-hz = /bits/ 64 <630000000 630000000 630000000 1104000000>; + required-opps = <&rpmhpd_opp_nom>, + <&rpmhpd_opp_turbo>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000 710000000 710000000 1260000000>; + required-opps = <&rpmhpd_opp_turbo>, + <&rpmhpd_opp_turbo_l1>; + }; + + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000 710000000 850000000 1260000000>; + required-opps = <&rpmhpd_opp_turbo>, + <&rpmhpd_opp_turbo_l3>; + }; + }; + }; -- 2.43.0