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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: A43eeVJ/ncF8ZzreD3/e7foK6ii6bzb4MTs8xLmLq0Un1LLtpKiJls4x4q55fAkGJlLs2yxLypNHPURGV/rL9jCBcPdg2Zek5gyoUAjVdwA907AiRUUEQw6wtswrZ6NXYVvoae/tpqYL68KL0PzF1JgO83fUnlQPY/+iIBli0X036pe8ga1mYRF+vras7+SZ0/VauIdwqhfcS5miY7Qrr77PBqOEpgejeP4Ie/P4RbaVB/CTKv70+gQh/kiM0PRz4p9aorBMQeAXPfVwSb88xzkMBL56q4R7qZMLZAj9FcoJ/M54rpGqedH+YkAvM6YegLnQlN8OrkVciSNI2/D+ZqfDNB4YiA0oLyIJtY7Jcs8JpZaGyxGzzysLsXzjDMkJU9IteG5IIwZw7nAs+p9B7ha5LD6gDvO1vgg2FsvXcdzGkHB5OTU/Qbaq7l0dCIIG X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Sep 2026 07:16:39.1841 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 97e00331-e268-427a-62c8-08df19429c71 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000037B7.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB9397 On Xilinx Versal NET, the ARM SMMUv3 EVENTQ, PRIQ and GERROR interrupts are routed through a vendor-specific Control and Status Register (CSR) block, where they must be enabled, cleared and acknowledged before being forwarded to the parent GIC. This series adds a small irqchip driver for the CSR block that chains to the standard arm-smmu-v3 driver, so the generic SMMUv3 driver needs no changes. Patch 1 adds the DT binding. Patch 2 adds the irqchip driver. Changes in v3: - irqchip driver (Sashiko): harden against interrupt sources left enabled/latched by a prior boot stage: - Mask and clear every CSR source at init, including CMD_SYNC (bit 1) which the driver does not service. - Gate the handler on the mask register (ISR & ~MASK) instead of the raw ISR, so masked-but-latched sources are not dispatched. - Mask and clear any active source with no mapped consumer so it cannot spin the parent line. - dt-bindings: No changes Link to v2: https://lore.kernel.org/all/20260918-smmu-changes-v2-v2-0-adda681ab983@amd.com/#t Changes in v2: - Posted as a proper threaded series with a cover letter (v1 patches went out individually). - dt-bindings (Krzysztof): - Dropped the irrelevant arm,smmu-v3 consumer node from the example. - Dropped the unused "smmu_irq_csr" label from the example. - Dropped the redundant "binding" from the patch subject. - irqchip driver (Thomas): - Aligned kernel-doc member descriptions and used "interrupt" instead of "IRQ". - Used guard(raw_spinlock)() in the mask/unmask/ack callbacks and addressed the comments related to lock handling. - Thomas suggested using devm-managed allocation and irqdomain APIs; however, the driver is registered via IRQCHIP_DECLARE() and has no associated struct device, so devm APIs cannot be used. This code is left unchanged. Link to v1: https://lore.kernel.org/all/20260817105233.1557748-1-tushar.nimkar@amd.com/ https://lore.kernel.org/all/20260817105251.1557770-1-tushar.nimkar@amd.com/ Signed-off-by: Tushar Nimkar --- Anirudha Sarangi (2): dt-bindings: interrupt-controller: Add Xilinx Versal NET SMMU CSR irqchip: Add Xilinx Versal NET SMMU CSR interrupt controller driver .../xlnx,versal-net-smmu-csr.yaml | 75 +++++++ MAINTAINERS | 10 + drivers/irqchip/Kconfig | 10 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-xilinx-smmu-csr.c | 247 +++++++++++++++++++++ 5 files changed, 343 insertions(+) --- base-commit: 0d9d0dbf2fddcff5859d623e90ca73c4054276e1 change-id: 20260917-smmu-changes-v2-9cf7435d6969 Best regards, -- Tushar Nimkar