[DRM] amdgpu: HDMI FreeSync not exposed on Samsung S22C31x despite AMD VSDB

["Ata İlhan Köktürk" <atailhan2006@gmail.com>]

Hi,

I am investigating an issue where HDMI FreeSync
is not exposed for a Samsung S22C31x monitor on
an AMD Picasso/Raven 2 GPU, although the monitor
advertises an AMD FreeSync range in its EDID and
VRR works under Windows.

Hardware/software:

* GPU: 03:00.0 VGA compatible controller [0300]:
Advanced Micro Devices, Inc. [AMD/ATI] Picasso/Raven 2
[Radeon Vega Series / Radeon Vega Mobile Series]
[1002:15d8] (rev c2)
* Kernel: 7.2.5-200.fc44
* Compositor: Sway (Wayland)
* Monitor: Samsung S22C31x
* Connector: HDMI-A-1
* EDID serial: H9DX100210
* Kernel command line includes: amdgpu.freesync_video=1

Observed:

* swaymsg -t get_outputs reports "Adaptive sync: disabled" for HDMI-A-1.
* Adaptive sync remains disabled at both 1920x1080@60 Hz and 1920x1080@75 Hz.
* The same monitor exposes and enables FreeSync under Windows.

The EDID contains the following AMD Vendor-Specific Data Block:

Vendor-Specific Data Block (AMD), OUI 00-00-1A:
    Version: 1
    Feature Caps: 0x01
    Minimum Refresh Rate: 48 Hz
    Maximum Refresh Rate: 75 Hz
    Flags 1.x: 0x00

The HDMI VSDB therefore appears to advertise a 48-75 Hz FreeSync range.

There is also this message in dmesg:

amdgpu 0000:03:00.0: [drm] Failed to setup vendor infoframe on connector HDMI-A-1: -22

I believe this is the -EINVAL path from
drm_hdmi_vendor_infoframe_from_display_mode() for this timing and
is probably unrelated to the FreeSync issue.

The part I am currently investigating is amdgpu_dm_update_freesync_caps().

For HDMI, the driver calls parse_hdmi_amd_vsdb(), which
on this DCN configuration goes through the DMUB path:

parse_hdmi_amd_vsdb()
  -> parse_edid_cea()
     -> parse_edid_cea_dmub()
        -> dm_edid_parser_send_cea()
           -> output->amd_vsdb.freesync_supported

If the DMUB parser returns freesync_supported == 0,
the driver does not expose the connector as VRR capable.

What makes this interesting is that the DRM EDID parser also
contains the corresponding AMD VSDB information in
connector->display_info.amd_vsdb, while the DMUB result
does not result in FreeSync being exposed.

I am wondering about the following:

1. Is the AMD VSDB layout above expected to be accepted by
the DMUB EDID parser, particularly with
Feature Caps 0x01, Flags 1.x == 0x00, and no MCCS VCP code byte?

2. If the DMUB parser rejects this form of AMD VSDB, should amdgpu_dm
fall back to the software-parsed connector->display_info.amd_vsdb
when determining FreeSync capability?

I have a working kernel tree and can run diagnostic tests
or test a small patch. I can also provide drm.debug
output or DMUB-related traces if useful.

Thanks,
Ata İlhan Köktürk