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Wed, 23 Sep 2026 00:23:52 -0700 From: Manikanta Maddireddy To: Lorenzo Pieralisi , Krzysztof Wilczynski , Manivannan Sadhasivam , "Bjorn Helgaas" , CC: Rob Herring , Thierry Reding , Jonathan Hunter , Kishon Vijay Abraham I , Frank Li , Vidya Sagar , Niklas Cassel , Koichiro Den , Marco Crivellari , "Andy Shevchenko" , , , "Manikanta Maddireddy" Subject: [PATCH 11/11] PCI: endpoint: test: Do not relocate fixed MSI-X tables Date: Wed, 23 Sep 2026 12:52:37 +0530 Message-ID: <20260923072237.1139013-12-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260923072237.1139013-1-mmaddireddy@nvidia.com> References: <20260923072237.1139013-1-mmaddireddy@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002313:EE_|DS2PR12MB101350:EE_ X-MS-Office365-Filtering-Correlation-Id: 0ce0e19c-c19a-4b0d-dd2d-08df1943a946 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|1800799024|36860700016|82310400026|23010399003|56012099006|6133799003|10067099003|5023799004|11063799006|18002099003|22082099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: ae73epnmYCKLjdrp3LKPwA/ULnnS/FK0XOTRWbJbP6fKJd2mRpj3F7brrePSzcDSf4rqHlPRwcDaAIv8PPi62+PKo8kHq1he8CE+XGhGw7bFALIQ03fCioHbDP33lu1D5xHD0lne3bLtVpoEylZM3rRTp+I5WWiXsJH/o6UIdXCVOl2SjAMibkrH9G1l7iNEw0h8wsnBXEd/p2YD7fK2Sw8RjGTYEoYdFZx26VjvZdfJKwlcKmzpD821WUxSSDrbssfc7AutMKKgCRywbJHbjIiLhOBNKasgLssD3IjR6Gb7R0rvL146naOgHfCuWmaL2/SFyCJ2H2AbygmLIhzoRrdHLp698BCLkbtkBEa6bLBa12aJWIdTZ3Aea0U2Ndh5tzJ4Sp5CcHKzxOOFj3scUraH4sqsTjaI6oX/FhoYcLd/YW5Kop+3DwenFGheuVSR X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Sep 2026 07:24:10.3134 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0ce0e19c-c19a-4b0d-dd2d-08df1943a946 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002313.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS2PR12MB101350 Some endpoint controllers expose MSI-X table/PBA storage at fixed, hardware-owned BARs. Such BARs are described to endpoint functions as BAR_RESERVED with PCI_EPC_BAR_RSVD_MSIX_TBL_RAM, so the function driver must not reprogram the MSI-X Table/PBA capability to point into ordinary function BAR memory. pci_epf_test always allocates MSI-X storage after its test registers and calls pci_epc_set_msix(). On controllers with fixed MSI-X storage, this overwrites the controller-defined MSI-X layout. For example, the generic DesignWare path derives the PBA offset from the number of vectors, which can make the host program the wrong MSI-X storage and prevent MSI-X delivery. Detect fixed MSI-X table BARs and leave the controller-owned MSI-X capability layout unchanged. Keep allocating and programming MSI-X storage in the test BAR only for controllers that do not advertise fixed MSI-X table storage. Signed-off-by: Manikanta Maddireddy --- drivers/pci/endpoint/functions/pci-epf-test.c | 27 +++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) diff --git a/drivers/pci/endpoint/functions/pci-epf-test.c b/drivers/pci/endpoint/functions/pci-epf-test.c index d4905aa8e4c0..82d4714e998c 100644 --- a/drivers/pci/endpoint/functions/pci-epf-test.c +++ b/drivers/pci/endpoint/functions/pci-epf-test.c @@ -83,6 +83,7 @@ struct pci_epf_test { struct config_group group; enum pci_barno test_reg_bar; size_t msix_table_offset; + bool msix_table_fixed; struct delayed_work cmd_handler; struct dma_chan *dma_chan_tx; struct dma_chan *dma_chan_rx; @@ -98,6 +99,26 @@ struct pci_epf_test { size_t bar_size[PCI_STD_NUM_BARS]; }; +static bool pci_epf_test_msix_table_fixed(const struct pci_epc_features *features) +{ + enum pci_barno bar; + int i; + + for (bar = BAR_0; bar < PCI_STD_NUM_BARS; bar++) { + const struct pci_epc_bar_desc *desc = &features->bar[bar]; + + if (desc->type != BAR_RESERVED) + continue; + + for (i = 0; i < desc->nr_rsvd_regions; i++) { + if (desc->rsvd_regions[i].type == PCI_EPC_BAR_RSVD_MSIX_TBL_RAM) + return true; + } + } + + return false; +} + struct pci_epf_test_reg { __le32 magic; __le32 command; @@ -1214,7 +1235,7 @@ static int pci_epf_test_epc_init(struct pci_epf *epf) } } - if (epc_features->msix_capable) { + if (epc_features->msix_capable && !epf_test->msix_table_fixed) { ret = pci_epc_set_msix(epc, epf->func_no, epf->vfunc_no, epf->msix_interrupts, epf_test->test_reg_bar, @@ -1282,7 +1303,9 @@ static int pci_epf_test_alloc_space(struct pci_epf *epf) test_reg_bar_size = ALIGN(sizeof(struct pci_epf_test_reg), 128); - if (epc_features->msix_capable) { + epf_test->msix_table_fixed = pci_epf_test_msix_table_fixed(epc_features); + + if (epc_features->msix_capable && !epf_test->msix_table_fixed) { msix_table_size = PCI_MSIX_ENTRY_SIZE * epf->msix_interrupts; epf_test->msix_table_offset = test_reg_bar_size; /* Align to QWORD or 8 Bytes */ -- 2.34.1