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Wed, 23 Sep 2026 00:23:02 -0700 From: Manikanta Maddireddy To: Lorenzo Pieralisi , Krzysztof Wilczynski , Manivannan Sadhasivam , "Bjorn Helgaas" , CC: Rob Herring , Thierry Reding , Jonathan Hunter , Kishon Vijay Abraham I , Frank Li , Vidya Sagar , Niklas Cassel , Koichiro Den , Marco Crivellari , "Andy Shevchenko" , , , "Manikanta Maddireddy" Subject: [PATCH 02/11] PCI: tegra194: Check core reset deassertion Date: Wed, 23 Sep 2026 12:52:28 +0530 Message-ID: <20260923072237.1139013-3-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260923072237.1139013-1-mmaddireddy@nvidia.com> References: <20260923072237.1139013-1-mmaddireddy@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001F1:EE_|SA3PR12MB8803:EE_ X-MS-Office365-Filtering-Correlation-Id: 3763568b-54cc-4bbd-2d3a-08df19438d70 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|7416014|376014|1800799024|82310400026|36860700016|6133799003|10067099003|11063799006|56012099006|18002099003|22082099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: NaMpSSpl64fkTdaOV1EYtTm2elW4M2kSer84HlaauaUKv8mK7W4itWXUGNF6DFhb8KuMuxr+jcam2xkxEIIg644NLRGHm+Yg+C2mbaPFym9hzeea1prHecqllzHVFGYWkWxbUDl+UyKUBHt0TAxcQ7IzfYFkneu3UxRkD5FiIqr2hUddnLra8FodzMaml12cunelGhi7X8aeT1Hd4wQmgU5/ZsjbZQ987EAQSWF3P5hshxS9Jvx2m95H3kwzOsb7uwxX2bpH25TXwrzOHqGlW37upZ8qHss4tF5/mK1PvZhTZqACnGGMHuk4i2EinVeNBWi1rb16puvmCeObz1IionX1UqGBzns9o3IGsPuabVBtbtph4XyoJDgp5OgIRDbAYn0tIXbuyxfejOgjMKZzMLf7yokfXmGA/PmSotYuqfpKs96LZzgQZUrb9tRujd+h X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Sep 2026 07:23:23.5625 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3763568b-54cc-4bbd-2d3a-08df19438d70 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F1.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB8803 Several paths access DBI registers after deasserting the controller core reset. If reset_control_deassert() fails, those DBI accesses can trigger a CBB timeout, or setup can return success with the core still in reset. Check core reset deassertion in Root Port setup, the DLF retry path and the Endpoint PERST# deassert path. Unwind before DBI access when deassertion fails. Fixes: 56e15a238d92 ("PCI: tegra: Add Tegra194 PCIe support") Signed-off-by: Manikanta Maddireddy --- drivers/pci/controller/dwc/pcie-tegra194.c | 23 +++++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index f2b75bf49a12..810695d8e5c8 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -954,6 +954,7 @@ static int tegra_pcie_dw_start_link(struct dw_pcie *pci) struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); struct dw_pcie_rp *pp = &pci->pp; u32 val, offset, tmp; + int ret; bool retry = true; if (pcie->of_data->mode == DW_PCIE_EP_TYPE) { @@ -1009,7 +1010,12 @@ static int tegra_pcie_dw_start_link(struct dw_pcie *pci) appl_writel(pcie, val, APPL_CTRL); reset_control_assert(pcie->core_rst); - reset_control_deassert(pcie->core_rst); + ret = reset_control_deassert(pcie->core_rst); + if (ret) { + dev_err(pci->dev, "Failed to deassert core reset: %d\n", + ret); + return ret; + } offset = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_DLF); val = dw_pcie_readl_dbi(pci, offset + PCI_DLF_CAP); @@ -1455,10 +1461,16 @@ static int tegra_pcie_config_controller(struct tegra_pcie_dw *pcie, pcie->atu_dma_res->start & APPL_CFG_IATU_DMA_BASE_ADDR_MASK, APPL_CFG_IATU_DMA_BASE_ADDR); - reset_control_deassert(pcie->core_rst); + ret = reset_control_deassert(pcie->core_rst); + if (ret) { + dev_err(pcie->dev, "Failed to deassert core reset: %d\n", ret); + goto fail_core_rst; + } return ret; +fail_core_rst: + tegra_pcie_disable_phy(pcie); fail_phy: reset_control_assert(pcie->core_apb_rst); fail_core_apb_rst: @@ -1853,7 +1865,11 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie) LTR_NOSNOOP_MSG_REQ; appl_writel(pcie, val, APPL_LTR_MSG_1); - reset_control_deassert(pcie->core_rst); + ret = reset_control_deassert(pcie->core_rst); + if (ret) { + dev_err(dev, "Failed to deassert core reset: %d\n", ret); + goto fail_core_rst; + } /* Perform cleanup that requires refclk and core reset deasserted */ pci_epc_deinit_notify(pcie->pci.ep.epc); @@ -1927,6 +1943,7 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie) fail_init_complete: reset_control_assert(pcie->core_rst); +fail_core_rst: tegra_pcie_disable_phy(pcie); fail_phy: reset_control_assert(pcie->core_apb_rst); -- 2.34.1