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Wed, 23 Sep 2026 00:23:18 -0700 From: Manikanta Maddireddy To: Lorenzo Pieralisi , Krzysztof Wilczynski , Manivannan Sadhasivam , "Bjorn Helgaas" , CC: Rob Herring , Thierry Reding , Jonathan Hunter , Kishon Vijay Abraham I , Frank Li , Vidya Sagar , Niklas Cassel , Koichiro Den , Marco Crivellari , "Andy Shevchenko" , , , "Manikanta Maddireddy" Subject: [PATCH 05/11] PCI: tegra194: Check for 16 GT/s capability before programming Date: Wed, 23 Sep 2026 12:52:31 +0530 Message-ID: <20260923072237.1139013-6-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260923072237.1139013-1-mmaddireddy@nvidia.com> References: <20260923072237.1139013-1-mmaddireddy@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BY1PEPF000264B2:EE_|CY8PR12MB8313:EE_ X-MS-Office365-Filtering-Correlation-Id: 1990208b-f461-41d4-b999-08df19439858 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|36860700016|23010399003|7416014|376014|10067099003|11063799006|6133799003|18002099003|22082099003|56012099006; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: RLAiE7KbkXI8TRbZ+W3OiUJMUBi8VnJO0dphcXYHmg2VP2igWSPDzMpMSafW4IpMCY31Uwk+DyksXNQrXdSDEs3xNOOtUkiWA4wzegTBH1+oBGmYTSBer0mbgvyRc/KStoq3IKqRuEyEo/nzWt+2ohZaYtt1Uopber0Gc6DfiXdvGIuI8v9uuJjthw3jzDhWVup+G6ZlWkQbqtGAX0Sipw2hXXeMhuUhQ4D1s0q6n7mgz/Oi6dQpsf8CpbkICtMEddoAeiMAc/HOm0lYH9yJ/zQWueXkfg4hUAo36X/oNY2tZkM98mj8KpcXxkIICgbD5R83tHPSFw2i7ceak5hhxwVycBaHg8h/2veWnRX2fN9lV0nZXGTYxCO5G4AOFh8k3kebdMAKz+e/EWVuPAZmU4mT0csKW+7g3l414bC1fO/mssngOfJyFhIq5ifX79Mj X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Sep 2026 07:23:41.7983 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1990208b-f461-41d4-b999-08df19439858 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BY1PEPF000264B2.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB8313 config_gen3_gen4_eq_presets() added PCI_PL_16GT_LE_CTRL to the result of dw_pcie_find_ext_capability() without checking whether the 16 GT/s capability exists. If the capability is absent, the code writes lane presets at an unrelated configuration offset. Look up the capability once before the lane loop and skip the 16 GT/s lane equivalent control programming when it is absent. Fixes: 56e15a238d92 ("PCI: tegra: Add Tegra194 PCIe support") Signed-off-by: Manikanta Maddireddy --- drivers/pci/controller/dwc/pcie-tegra194.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index aa47052a37cf..358156c63da0 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -840,7 +840,11 @@ static void tegra_pcie_enable_interrupts(struct dw_pcie_rp *pp) static void config_gen3_gen4_eq_presets(struct tegra_pcie_dw *pcie) { struct dw_pcie *pci = &pcie->pci; - u32 val, offset, i; + u32 pl16g, val, i; + + pl16g = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_PL_16GT); + if (pl16g) + pl16g += PCI_PL_16GT_LE_CTRL; /* Program init preset */ for (i = 0; i < pcie->num_lanes; i++) { @@ -851,15 +855,15 @@ static void config_gen3_gen4_eq_presets(struct tegra_pcie_dw *pcie) GEN3_GEN4_EQ_PRESET_INIT); dw_pcie_writew_dbi(pci, CAP_SPCIE_CAP_OFF + (i * 2), val); - offset = dw_pcie_find_ext_capability(pci, - PCI_EXT_CAP_ID_PL_16GT) + - PCI_PL_16GT_LE_CTRL; - val = dw_pcie_readb_dbi(pci, offset + i); + if (!pl16g) + continue; + + val = dw_pcie_readb_dbi(pci, pl16g + i); FIELD_MODIFY(PCI_PL_16GT_LE_CTRL_DSP_TX_PRESET_MASK, &val, GEN3_GEN4_EQ_PRESET_INIT); FIELD_MODIFY(PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_MASK, &val, GEN3_GEN4_EQ_PRESET_INIT); - dw_pcie_writeb_dbi(pci, offset + i, val); + dw_pcie_writeb_dbi(pci, pl16g + i, val); } val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); -- 2.34.1