From: Rosen Penev <rosenp@gmail.com>
To: devicetree@vger.kernel.org
Cc: Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>, Ray Jui <rjui@broadcom.com>,
Scott Branden <sbranden@broadcom.com>,
Broadcom internal kernel review list
<bcm-kernel-feedback-list@broadcom.com>,
linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM
IPROC ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list)
Subject: [PATCH] ARM: dts: alamo: use qca8337 internal PHYs
Date: Wed, 23 Sep 2026 11:39:12 -0700 [thread overview]
Message-ID: <20260923183912.13389-1-rosenp@gmail.com> (raw)
The QCA8337 switch has a managed internal MDIO bus for its built-in
PHYs. Move the PHY nodes from the external mdio@0 bus into a
subnode of the switch, and mark the connected switch ports with
phy-mode = "internal", so the ports are linked to the correct PHYs.
Assisted-by: LLM
Signed-off-by: Rosen Penev <rosenp@gmail.com>
---
.../dts/broadcom/bcm958625-meraki-alamo.dtsi | 100 +++++++++++-------
1 file changed, 60 insertions(+), 40 deletions(-)
diff --git a/arch/arm/boot/dts/broadcom/bcm958625-meraki-alamo.dtsi b/arch/arm/boot/dts/broadcom/bcm958625-meraki-alamo.dtsi
index c54451dde6dd..d0199c07707c 100644
--- a/arch/arm/boot/dts/broadcom/bcm958625-meraki-alamo.dtsi
+++ b/arch/arm/boot/dts/broadcom/bcm958625-meraki-alamo.dtsi
@@ -85,26 +85,6 @@ mdio@0 {
#address-cells = <1>;
#size-cells = <0>;
- phy_port6: phy@0 {
- reg = <0>;
- };
-
- phy_port7: phy@1 {
- reg = <1>;
- };
-
- phy_port8: phy@2 {
- reg = <2>;
- };
-
- phy_port9: phy@3 {
- reg = <3>;
- };
-
- phy_port10: phy@4 {
- reg = <4>;
- };
-
switch@10 {
compatible = "qca,qca8337";
reg = <0x10>;
@@ -128,60 +108,70 @@ fixed-link {
port@1 {
reg = <1>;
label = "lan8";
+ phy-mode = "internal";
phy-handle = <&phy_port6>;
};
port@2 {
reg = <2>;
label = "lan9";
+ phy-mode = "internal";
phy-handle = <&phy_port7>;
};
port@3 {
reg = <3>;
label = "lan10";
+ phy-mode = "internal";
phy-handle = <&phy_port8>;
};
port@4 {
reg = <4>;
label = "lan11";
+ phy-mode = "internal";
phy-handle = <&phy_port9>;
};
port@5 {
reg = <5>;
label = "lan12";
+ phy-mode = "internal";
phy-handle = <&phy_port10>;
};
};
- };
- };
- mdio-mii@2000 {
- reg = <0x2000>;
- #address-cells = <1>;
- #size-cells = <0>;
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
- phy_port1: phy@0 {
- reg = <0>;
- };
+ phy_port6: ethernet-phy@0 {
+ reg = <0>;
+ };
- phy_port2: phy@1 {
- reg = <1>;
- };
+ phy_port7: ethernet-phy@1 {
+ reg = <1>;
+ };
- phy_port3: phy@2 {
- reg = <2>;
- };
+ phy_port8: ethernet-phy@2 {
+ reg = <2>;
+ };
- phy_port4: phy@3 {
- reg = <3>;
- };
+ phy_port9: ethernet-phy@3 {
+ reg = <3>;
+ };
- phy_port5: phy@4 {
- reg = <4>;
+ phy_port10: ethernet-phy@4 {
+ reg = <4>;
+ };
+ };
};
+ };
+
+ mdio-mii@2000 {
+ reg = <0x2000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
switch@10 {
compatible = "qca,qca8337";
@@ -206,33 +196,63 @@ fixed-link {
port@1 {
reg = <1>;
label = "lan3";
+ phy-mode = "internal";
phy-handle = <&phy_port1>;
};
port@2 {
reg = <2>;
label = "lan4";
+ phy-mode = "internal";
phy-handle = <&phy_port2>;
};
port@3 {
reg = <3>;
label = "lan5";
+ phy-mode = "internal";
phy-handle = <&phy_port3>;
};
port@4 {
reg = <4>;
label = "lan6";
+ phy-mode = "internal";
phy-handle = <&phy_port4>;
};
port@5 {
reg = <5>;
label = "lan7";
+ phy-mode = "internal";
phy-handle = <&phy_port5>;
};
};
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy_port1: ethernet-phy@0 {
+ reg = <0>;
+ };
+
+ phy_port2: ethernet-phy@1 {
+ reg = <1>;
+ };
+
+ phy_port3: ethernet-phy@2 {
+ reg = <2>;
+ };
+
+ phy_port4: ethernet-phy@3 {
+ reg = <3>;
+ };
+
+ phy_port5: ethernet-phy@4 {
+ reg = <4>;
+ };
+ };
};
};
};
--
2.55.0
reply other threads:[~2026-09-23 18:39 UTC|newest]
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