From: Taniya Das <taniya.das@oss.qualcomm.com>
To: Bjorn Andersson <andersson@kernel.org>,
Stephen Boyd <sboyd@kernel.org>,
Brian Masney <bmasney+clk@redhat.com>,
Jerome Brunet <jbrunet+clk@baylibre.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Shawn Guo <shengchao.guo@oss.qualcomm.com>,
Abel Vesa <abelvesa@kernel.org>
Cc: Ajit Pandey <ajit.pandey@oss.qualcomm.com>,
Imran Shaik <imran.shaik@oss.qualcomm.com>,
Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com>,
linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
Taniya Das <taniya.das@oss.qualcomm.com>,
Abel Vesa <abel.vesa@oss.qualcomm.com>
Subject: [PATCH v2 0/3] clk: qcom: Add Nord DPRX clock controller support
Date: Thu, 24 Sep 2026 00:51:30 +0530 [thread overview]
Message-ID: <20260924-nords_dprx-v2-0-fa4364e087ef@oss.qualcomm.com> (raw)
Add support for the DisplayPort Receiver (DPRX) clock controllers found
on Qualcomm Nord devices. There are two identical DPRX clock controller
instances (DPRX0 and DPRX1), each providing clocks for the DPRX core,
audio, AHB and video memory paths, along with their core PLLs.
The DPRX PLLs are ZONDA_OLE instances whose PLL_ALPHA_VAL register has
been widened to 28 bits to carry the fractional word at a finer
resolution. The existing alpha-PLL core derives the ALPHA_VAL width
solely from the register-map layout and can only express 16 or 40 bits,
so the first patch adds an optional per-PLL alpha_width override that,
when set, feeds the recalc_rate/round_rate scaling and the Zonda
set_rate L-adjust MSB check. This is a prerequisite for the DPRX PLLs to
lock to and report the correct rate.
The series is organised as follows:
- Patch 1 - alpha-PLL 28-bit ALPHA_VAL width.
- Patch 2 - documents the Nord DPRX clock controller device tree
bindings.
- Patch 3 - adds the two DPRX clock controller drivers.
Changes in v2:
- Address review comments: remove unused definitions and includes, rewrap the
alpha-width ternary, and clarify that DPRXCC provides clocks and resets.
- Add RB-by tag [Abel]
- Link to v1: https://lore.kernel.org/r/20260907-nords_dprx-v1-0-d472af3f01b1@oss.qualcomm.com
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
---
Taniya Das (3):
clk: qcom: clk-alpha-pll: support a 28-bit ALPHA_VAL width
dt-bindings: clock: qcom: document the Nord DPRX Clock Controller
clk: qcom: dprxcc: Add Nord DPRX clock controller support
.../bindings/clock/qcom,nord-dprxcc.yaml | 68 ++++
drivers/clk/qcom/Kconfig | 11 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/clk-alpha-pll.c | 8 +-
drivers/clk/qcom/clk-alpha-pll.h | 3 +
drivers/clk/qcom/dprxcc0-nord.c | 434 +++++++++++++++++++++
drivers/clk/qcom/dprxcc1-nord.c | 433 ++++++++++++++++++++
include/dt-bindings/clock/qcom,nord-dprxcc.h | 27 ++
8 files changed, 981 insertions(+), 4 deletions(-)
---
base-commit: a8c591ed6b672915e0be57843f943a2a723aff40
change-id: 20260903-nords_dprx-4903d7acc841
Best regards,
--
Taniya Das <taniya.das@oss.qualcomm.com>
next reply other threads:[~2026-09-23 19:21 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-23 19:21 Taniya Das [this message]
2026-09-23 19:21 ` [PATCH v2 1/3] clk: qcom: clk-alpha-pll: support a 28-bit ALPHA_VAL width Taniya Das
2026-09-24 8:50 ` Shawn Guo
2026-09-23 19:21 ` [PATCH v2 2/3] dt-bindings: clock: qcom: document the Nord DPRX Clock Controller Taniya Das
2026-09-24 8:56 ` Shawn Guo
2026-09-24 8:57 ` Taniya Das
2026-09-23 19:21 ` [PATCH v2 3/3] clk: qcom: dprxcc: Add Nord DPRX clock controller support Taniya Das
2026-09-24 9:05 ` Shawn Guo
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20260924-nords_dprx-v2-0-fa4364e087ef@oss.qualcomm.com \
--to=taniya.das@oss.qualcomm.com \
--cc=abel.vesa@oss.qualcomm.com \
--cc=abelvesa@kernel.org \
--cc=ajit.pandey@oss.qualcomm.com \
--cc=andersson@kernel.org \
--cc=bmasney+clk@redhat.com \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=imran.shaik@oss.qualcomm.com \
--cc=jagadeesh.kona@oss.qualcomm.com \
--cc=jbrunet+clk@baylibre.com \
--cc=krzk+dt@kernel.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=robh@kernel.org \
--cc=sboyd@kernel.org \
--cc=shengchao.guo@oss.qualcomm.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®