From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9C60F3932D9 for ; Thu, 24 Sep 2026 06:10:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790230236; cv=none; b=QshDYIBskOoYZIIKkTFXF+SGsCV/mwv0zHWIskhQi1YPC+CGUYf1buCnOyV4t8XLQh5P5WJreJUhfrBhJPiznJJwrt7rJLIxdr7WgPp7fhzliTFOUjV6dF0MGIK/lvchcouLvy7I3PnakZxZMY/xEkIR5eGLKwODEQ9FV1MZ6Nk= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790230236; c=relaxed/simple; bh=4YaiRj0EruogM3vB6ar/BqOcXs5wxkMYrvnCtxPKVyo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=IzHgbqxusTtzjQ/QpxDosidSxLp/aXUZkLOlo65YMMRHlMSsc9Vuu/dev+QZrDSbs5XU8/HS5bXfIOVXxtuB0ea3ixgLakG3M92ImhvU5p8LT6caPMmdnDFXtEop6bPN65TMvDwQACVTXF/B43YJazT7Z1PuLyHcKx/gYRGx940= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=ozwOpvG4; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=Z4LBmu5m; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="ozwOpvG4"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="Z4LBmu5m" Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 68O5eGFG2277216 for ; Thu, 24 Sep 2026 06:10:33 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= O4tnRt+BeNXcNiBvIio1lUad6y6QIIHL7crYNQLh6M0=; b=ozwOpvG4MLkdi46U vELvIOknLnl5FBe/v7PSs55pHCyIScp8kWceE51kBG8Z/wpk0UonIuodenxKKk7u wdqA1cv0nbVfviJr/YeWM6Cbt8zJt1edhlafblYf6zk7YNa5o0XY9RWU3lHDboDT JgBzPWPpNPZ9h8h1IXJh+w00Bl5SvjuJ1AVNwsU5a5WhKJ1SOrx0UfTBOq/ES/7g O5+xdPGDbERW5HCDZUZkdYgFS6NDfcYGFfHDoDaZCiHi8Rk+WphKdHTYAe6qEaKQ Du6aCSJGjV+iSx827kRNC9NzVty6lLZNZV+VG9LcEIuU+mB+dLYnsNIVrxjwwrc3 IqLrvw== Received: from mail-dl1-f69.google.com (mail-dl1-f69.google.com [74.125.82.69]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4gvfjxuj60-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 24 Sep 2026 06:10:33 +0000 (GMT) Received: by mail-dl1-f69.google.com with SMTP id a92af1059eb24-143826c4a13so1717787c88.1 for ; Wed, 23 Sep 2026 23:10:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1790230233; x=1790835033; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=O4tnRt+BeNXcNiBvIio1lUad6y6QIIHL7crYNQLh6M0=; b=Z4LBmu5mJfhE+qBFI8rDE+eWGQc8MWLn7/gvGa1R1rvQMRFg1LkhY1Qjpe+JJ3qY4D qAYlcTM6+x8tBhGeU+aHesD4WhN4RpcgrxOBvLusI2l+aMMBn8EI0i0vexbG1DyZNiP5 Ktz5SRrHnnhTI1jhy22G8TSc2u49LGJHflhPw4TMfJRGASG1gccZkWPEPvneNw6UH6Qc sxJQ5AGehCJTTbCgQLbwOwvPad3BcbwWJV5luMLpR+0KY9EkaNZ4VL0jUvdTxI4RVTaz omW0t9rKT5VsdVrPiO58eDf+m9APIH5qItvX12S0SZat7cZJAdlulC3Ffonars6uPm/m XE5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20260707; t=1790230233; x=1790835033; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=O4tnRt+BeNXcNiBvIio1lUad6y6QIIHL7crYNQLh6M0=; b=umpfS+3y2gvkqKusxYIXHLUruLJbn66cWDmT+yWJJ7lKxBiDuDRgMebhoVdxcT5CKa jhFgQnAnXNpFtmE5kkasMX4lNlkERVYALmPcU+ntEvGp62B8WW3vPPLsGjDMkQqdCOFc 4Jtz7pqyYxMUyycZWyeS03q+pOltYCyvkKYo5ZNwZuzBGg7PGdXvf8SOfauppDsaDt+7 L3jhtrZtWM5nn6rkniVsJSi3nxMFOKRprOgDMTDCrlOJJA6+iZIp+cUYSZKd26oFumUa Iiih4Qu3bkoWrfOHgSOhiP/4YaeM2QoILvNw8c8v7lWtAOg3fRozEzy3DYM8VwxwAREM x2nw== X-Forwarded-Encrypted: i=1; AKwUvBy6UECLMAeROw/i86HQl4xY1aqoECiHOxlKZLC/MpDAQ74Mx0PZKI70zo1pBY1GXxvzSpRfA/m2kwMaidU=@vger.kernel.org X-Gm-Message-State: AFuF++mqOl3iHyrp85ITVdLpiSrqVwM3noxMSWGItXI7W3ChUic3Bx7Y Y/ZfUlNTEGEptseh+LHw3bkERuCMvvT0c/JFtJEfK1k5L6jeUPu/hrgkU558JhVeqY0HOT+e9hB /wBbYuIjYL2lB+Ta5w7ZmhL3Kupx8Li+KE3Rrq592FdE3aDp+sRuZRJ+NHnLDiQY1WO4= X-Gm-Gg: AYBFou0vNmFXqvQaylt9RDnYwM/lANPiBT+kfGXmMjMCzCJeiij68ScFxNQOPtBM7mY AKYJYhn7zwBhNyLvL8178koRCi+EioKPtX17jZ3Ipr9lQ1stAvuLvtNgCqBeU0A4aRB0JFnsCAY t8KunYc2E94x4urmSwuchrfwxkBHtfUA1lGl7e+X3AvGk/TWYcr3f7Vz8Oii0ah/qI4v6EFkysO iPDffVtc4TQHdA6iPMP6kttnAWpTf+dRSeRdGlCYzpgX2EkMw9crHUCpug8wmjNEICM45ViApWi e+1HiFtecS3957Rfs8nag8Na/RWePiSZzphu/KA7+uZLLB1H9Dm9DCIn9ujkoVbxYzFKdXd7Do5 NCWJSGdtoFCCyyKenW/9eyPClHmm2CL4vvzhc/IxCeK6ahci33jKwIpJNfev8MCPZVqoHRcDNpN K1WRSN29nr06XzurFPI08tLVvSbfld X-Received: by 2002:a05:7023:a5c:20b0:144:fb87:5b91 with SMTP id a92af1059eb24-14503fee63amr1043961c88.44.1790230232617; Wed, 23 Sep 2026 23:10:32 -0700 (PDT) X-Received: by 2002:a05:7023:a5c:20b0:144:fb87:5b91 with SMTP id a92af1059eb24-14503fee63amr1043916c88.44.1790230231977; Wed, 23 Sep 2026 23:10:31 -0700 (PDT) Received: from hu-varada-blr.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com. [103.229.18.19]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-144f9895c1asm10197680c88.12.2026.09.23.23.10.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Sep 2026 23:10:31 -0700 (PDT) From: Varadarajan Narayanan Date: Thu, 24 Sep 2026 11:40:04 +0530 Subject: [PATCH v3 3/5] phy: qcom: qmp-usb: Add IPQ9650 USB3 PHY configuration Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260924-phy-v3-3-088e7be0cfaa@oss.qualcomm.com> References: <20260924-phy-v3-0-088e7be0cfaa@oss.qualcomm.com> In-Reply-To: <20260924-phy-v3-0-088e7be0cfaa@oss.qualcomm.com> To: Vinod Koul , Neil Armstrong , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Wesley Cheng , Manu Gautam , Stephen Boyd , Philipp Zabel Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Varadarajan Narayanan , Abel Vesa X-Mailer: b4 0.14.3 X-Proofpoint-ORIG-GUID: 9tL-uczikuh59Trav3RUWaeQ575je3XC X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTI0MDAyNiBTYWx0ZWRfXwR3c8HnJq//n /3s1VoB9DEH6U84FC8t4TWmGfEO91jjGLQk3pN69V3TZunlDd8QTWnEPfoznPrRh7hKYH9Da7TQ 7X8DsN/nNQhYjbORJBxjciQCQ1NzJusnwNf5DLQwkDTepS3dn88z4DWXpSXDgDmK6kDQpspwx1G Bsq0b6HcnwbLxuo2oxvv7r0hLaRA/hWCEk6hiVWj3ZBFGLgCqYfg/gkZLhS6OHUXkbRHBpZbNW1 9EzSxZj75YOh9yAqBjI7pKtJUqBEY8qIjDxQ2FKzuyA2QgPm6fWHR6x53drqdxtLl7iCvmqOg0L xUmAeuKtK6+1VTZn8ytGRYjnRdOkPsC7NN35kq9/Jr1YdSBTC5ugGsbgs+RRv4D47CQ1/lrTyVp wcoIbj/RP4/3Nt5fFgBjPLPwoMvdk94E9PsDLwUwhzASsavwr7i5WKDZHHOajMUuv3FBpIf3Yn6 HIoiH36YZPG7S7TFnCw== X-Proofpoint-GUID: 9tL-uczikuh59Trav3RUWaeQ575je3XC X-Authority-Analysis: v=2.4 cv=NLpAaE6g c=1 sm=1 tr=0 ts=6ab4bed9 cx=c_pps a=kVLUcbK0zfr7ocalXnG1qA==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=1pfUWIqQpZhN5ooAS-4A:9 a=QEXdDO2ut3YA:10 a=vr4QvYf-bLy2KjpDp97w:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwOTI0MDAyNiBTYWx0ZWRfX/VOhEcANxbhm wO5OjaJ3UqLVC3gsrPYKTmBdwiEnnsByHmZJDRgTJbbIKgBD26nLhpCHtNg4U0lCD3UfAzMWT4d /PJociG849aNcpvgMGyaBjko6mWhvPU= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-24_02,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 bulkscore=0 adultscore=0 suspectscore=0 priorityscore=1501 impostorscore=0 clxscore=1015 lowpriorityscore=0 malwarescore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609240026 Add the USB3 QMP PHY configuration for IPQ9650, including the SoC-specific init tables and compatible data. IPQ9650 uses settings that do not match any existing supported SoC, so add a dedicated configuration to allow the driver to support it. Reviewed-by: Abel Vesa Signed-off-by: Varadarajan Narayanan --- drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 118 ++++++++++++++++++++++++++++++++ 1 file changed, 118 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c index b0790bcf0bc8..e772e1fa27cf 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c @@ -400,6 +400,101 @@ static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = { QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f), }; +static const struct qmp_phy_init_tbl ipq9650_usb3_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x7d), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xd4), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x68), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xaa), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE0, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xa2), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x01), +}; + +static const struct qmp_phy_init_tbl ipq9650_usb3_tx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xb5), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x00), +}; + +static const struct qmp_phy_init_tbl ipq9650_usb3_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x11), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe4), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x64), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xf6), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x89), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x35), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), +}; + +static const struct qmp_phy_init_tbl ipq9650_usb3_pcs_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x03), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL2, 0x83), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL1, 0x02), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNT_VAL_L, 0x09), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNT_VAL_H_TOL, 0xa2), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_MAN_CODE, 0x40), +}; + +static const struct qmp_phy_init_tbl ipq9650_usb3_pcs_usb_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), +}; + static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_V2_COM_SYSCLK_EN_SEL, 0x14), QMP_PHY_INIT_CFG(QSERDES_V2_COM_BIAS_EN_CLKBUFLR_EN, 0x08), @@ -1596,6 +1691,26 @@ static const struct qmp_phy_cfg ipq9574_usb3phy_cfg = { .regs = qmp_v3_usb3phy_regs_layout, }; +static const struct qmp_phy_cfg ipq9650_usb3phy_cfg = { + .offsets = &qmp_usb_offsets_v4, + + .serdes_tbl = ipq9650_usb3_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(ipq9650_usb3_serdes_tbl), + .tx_tbl = ipq9650_usb3_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(ipq9650_usb3_tx_tbl), + .rx_tbl = ipq9650_usb3_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(ipq9650_usb3_rx_tbl), + .pcs_tbl = ipq9650_usb3_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(ipq9650_usb3_pcs_tbl), + .pcs_usb_tbl = ipq9650_usb3_pcs_usb_tbl, + .pcs_usb_tbl_num = ARRAY_SIZE(ipq9650_usb3_pcs_usb_tbl), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = qmp_v4_usb3phy_regs_layout, + + .has_pwrdn_delay = true, +}; + static const struct qmp_phy_cfg msm8996_usb3phy_cfg = { .offsets = &qmp_usb_offsets_v3_msm8996, @@ -2483,6 +2598,9 @@ static const struct of_device_id qmp_usb_of_match_table[] = { }, { .compatible = "qcom,ipq9574-qmp-usb3-phy", .data = &ipq9574_usb3phy_cfg, + }, { + .compatible = "qcom,ipq9650-qmp-usb3-phy", + .data = &ipq9650_usb3phy_cfg, }, { .compatible = "qcom,msm8996-qmp-usb3-phy", .data = &msm8996_usb3phy_cfg, -- 2.34.1