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AKwUvBy/HltLi89NWcS5cIcQHiICiFof6gPj0F8H2mVfzlGfDkpo8P78t5kQP+6/2zotezK/9kfJkMlxHSs+Dig=@vger.kernel.org X-Gm-Message-State: AFuF++mQW/fXuYFderjhrqbx6iZuTjynj93Wv1DUH+3RFQxiUijlFKoZ zZ99duOLqerWKlUxL8JiNV3mJIfw809FEwMcitHjzJPlHjTJjD+zBBTcP7Lk3GfDNcXNc+dA8vV rX/XsIFHy3w== X-Received: from dlbrj21.prod.google.com ([2002:a05:7022:f415:b0:143:c6c8:ff2c]) (user=irogers job=prod-delivery.src-stubby-dispatcher) by 2002:a05:7022:6199:b0:144:c122:6cc7 with SMTP id a92af1059eb24-1450404309cmr1545219c88.33.1790228305989; Wed, 23 Sep 2026 22:38:25 -0700 (PDT) Date: Wed, 23 Sep 2026 22:36:38 -0700 In-Reply-To: <20260924053645.3555041-1-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260924053645.3555041-1-irogers@google.com> X-Mailer: git-send-email 2.56.0.rc1.310.g51773c2048-goog Message-ID: <20260924053645.3555041-15-irogers@google.com> Subject: [PATCH v1 14/21] perf vendor events intel: Update meteorlake events from 1.22 to 1.23 From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark , "=?UTF-8?q?Andreas=20F=C3=A4rber?=" , Manivannan Sadhasivam , Dapeng Mi , Chun-Tse Shao , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable The updated events were published in: https://github.com/intel/perfmon/commit/9020a281323a0fb26ee464b3be6e29465= 73cb963 Signed-off-by: Ian Rogers --- tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- tools/perf/pmu-events/arch/x86/meteorlake/other.json | 10 ++++++++++ .../perf/pmu-events/arch/x86/meteorlake/pipeline.json | 6 +++--- 3 files changed, 14 insertions(+), 4 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-ev= ents/arch/x86/mapfile.csv index 694359197777..15772f0b1cb1 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -23,7 +23,7 @@ GenuineIntel-6-3E,v24,ivytown,core GenuineIntel-6-2D,v24,jaketown,core GenuineIntel-6-(57|85),v16,knightslanding,core GenuineIntel-6-BD,v1.26,lunarlake,core -GenuineIntel-6-(AA|AC|B5),v1.22,meteorlake,core +GenuineIntel-6-(AA|AC|B5),v1.23,meteorlake,core GenuineIntel-6-1[AEF],v4,nehalemep,core GenuineIntel-6-2E,v4,nehalemex,core GenuineIntel-6-(CC|D5|E5),v1.07,pantherlake,core diff --git a/tools/perf/pmu-events/arch/x86/meteorlake/other.json b/tools/p= erf/pmu-events/arch/x86/meteorlake/other.json index 8320ffd83c51..5d1882064ff9 100644 --- a/tools/perf/pmu-events/arch/x86/meteorlake/other.json +++ b/tools/perf/pmu-events/arch/x86/meteorlake/other.json @@ -28,6 +28,16 @@ "UMask": "0x1", "Unit": "cpu_atom" }, + { + "BriefDescription": "Increments whenever there is an update to the= LBR array. [This event is alias to MISC_RETIRED.LBR_INSERTS]", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xcc", + "EventName": "LBR_INSERTS.ANY", + "PublicDescription": "Increments when an entry is added to the Las= t Branch Record (LBR) array (or removed from the array in case of RETURNs i= n call stack mode). The event requires LBR enable via IA32_DEBUGCTL MSR and= branch type selection via MSR_LBR_SELECT. [This event is alias to MISC_RET= IRED.LBR_INSERTS]", + "SampleAfterValue": "100003", + "UMask": "0x20", + "Unit": "cpu_core" + }, { "BriefDescription": "Counts streaming stores which modify a full 6= 4 byte cacheline that have any type of response.", "Counter": "0,1,2,3,4,5,6,7", diff --git a/tools/perf/pmu-events/arch/x86/meteorlake/pipeline.json b/tool= s/perf/pmu-events/arch/x86/meteorlake/pipeline.json index 6cd1b1659ec7..59a0a794e078 100644 --- a/tools/perf/pmu-events/arch/x86/meteorlake/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/meteorlake/pipeline.json @@ -909,7 +909,7 @@ "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc0", "EventName": "INST_RETIRED.REP_ITERATION", - "PublicDescription": "Number of iterations of Repeat (REP) string = retired instructions such as MOVS, CMPS, and SCAS. Each has a byte, word, a= nd doubleword version and string instructions can be repeated using a repet= ition prefix, REP, that allows their architectural execution to be repeated= a number of times as specified by the RCX register. Note: Since the number= of iterations within a REP instruction can be significantly affected by fa= st strings, this event may vary run to run and not match the architectural = number of iterations (specified by RCX)", + "PublicDescription": "Number of iterations of Repeat (REP) string = retired instructions such as MOVS, CMPS, and SCAS. Each has a byte, word, a= nd doubleword version and string instructions can be repeated using a repet= ition prefix, REP, that allows their architectural execution to be repeated= a number of times as specified by the RCX register. Note: Since the number= of iterations within a REP instruction can be significantly affected by fa= st strings, this event may vary from run to run and not match the architect= ural number of iterations (specified by RCX).", "SampleAfterValue": "2000003", "UMask": "0x8", "Unit": "cpu_core" @@ -1337,11 +1337,11 @@ "Unit": "cpu_atom" }, { - "BriefDescription": "Increments whenever there is an update to the= LBR array.", + "BriefDescription": "Increments whenever there is an update to the= LBR array. [This event is alias to LBR_INSERTS.ANY]", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xcc", "EventName": "MISC_RETIRED.LBR_INSERTS", - "PublicDescription": "Increments when an entry is added to the Las= t Branch Record (LBR) array (or removed from the array in case of RETURNs i= n call stack mode). The event requires LBR enable via IA32_DEBUGCTL MSR and= branch type selection via MSR_LBR_SELECT.", + "PublicDescription": "Increments when an entry is added to the Las= t Branch Record (LBR) array (or removed from the array in case of RETURNs i= n call stack mode). The event requires LBR enable via IA32_DEBUGCTL MSR and= branch type selection via MSR_LBR_SELECT. [This event is alias to LBR_INSE= RTS.ANY]", "SampleAfterValue": "100003", "UMask": "0x20", "Unit": "cpu_core" --=20 2.56.0.rc1.310.g51773c2048-goog