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AKwUvBzQJFh5zqByavO7rXRRmNeTJw7BxEAtYGwuwkTz7xI3ZCM6hQMfC0N9ehTn2sQWy1G2HQNPKj2gIZGPUp0=@vger.kernel.org X-Gm-Message-State: AFuF++mZCmdnZzaa/nEN9Ek5/ixyL2glM52D/BpvRCFvptYA6cQtHmp5 VOHzmaA8oPx8nDJ/6AmFafWJv6UYzXXImm95Ni/5cJkMZk2MM12dk/c3Tr4kI8/jD2rkiJWKWFH /lmxBUMsGfQ== X-Received: from dyvs26.prod.google.com ([2002:a05:693c:42da:b0:33c:28de:54ad]) (user=irogers job=prod-delivery.src-stubby-dispatcher) by 2002:a05:693c:69d9:b0:33e:d4ae:e10e with SMTP id 5a478bee46e88-34007382407mr1012666eec.40.1790228279493; Wed, 23 Sep 2026 22:37:59 -0700 (PDT) Date: Wed, 23 Sep 2026 22:36:27 -0700 In-Reply-To: <20260924053645.3555041-1-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260924053645.3555041-1-irogers@google.com> X-Mailer: git-send-email 2.56.0.rc1.310.g51773c2048-goog Message-ID: <20260924053645.3555041-4-irogers@google.com> Subject: [PATCH v1 03/21] perf vendor events intel: Update arrowlake events from 1.20 to 1.21 From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark , "=?UTF-8?q?Andreas=20F=C3=A4rber?=" , Manivannan Sadhasivam , Dapeng Mi , Chun-Tse Shao , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable The updated events were published in: https://github.com/intel/perfmon/commit/335239ef9a63a3a6e198233678f898761= cba38aa Signed-off-by: Ian Rogers --- .../pmu-events/arch/x86/arrowlake/other.json | 19 +++++++++++++++++++ .../arch/x86/arrowlake/pipeline.json | 8 ++++---- tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- 3 files changed, 24 insertions(+), 5 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/arrowlake/other.json b/tools/pe= rf/pmu-events/arch/x86/arrowlake/other.json index c8feed3a99a6..96086e257a6a 100644 --- a/tools/perf/pmu-events/arch/x86/arrowlake/other.json +++ b/tools/perf/pmu-events/arch/x86/arrowlake/other.json @@ -101,6 +101,25 @@ "UMask": "0x10", "Unit": "cpu_atom" }, + { + "BriefDescription": "Counts the number of LBR entries recorded. Re= quires LBRs to be enabled in IA32_LBR_CTL. [This event is alias to MISC_RET= IRED.LBR_INSERTS]", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xe4", + "EventName": "LBR_INSERTS.ANY", + "SampleAfterValue": "1000003", + "UMask": "0x1", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "LBR record is inserted [This event is alias t= o MISC_RETIRED.LBR_INSERTS]", + "Counter": "0,1,2,3,4,5,6,7,8,9", + "EventCode": "0xe4", + "EventName": "LBR_INSERTS.ANY", + "PublicDescription": "LBR record is inserted [This event is alias = to MISC_RETIRED.LBR_INSERTS] Available PDIST counters: 0,1", + "SampleAfterValue": "1000003", + "UMask": "0x1", + "Unit": "cpu_core" + }, { "BriefDescription": "This event is deprecated. [This event is alia= s to MISC_RETIRED.LBR_INSERTS]", "Counter": "0,1,2,3,4,5,6,7", diff --git a/tools/perf/pmu-events/arch/x86/arrowlake/pipeline.json b/tools= /perf/pmu-events/arch/x86/arrowlake/pipeline.json index 1f1b5a88216a..4afc90dfe96b 100644 --- a/tools/perf/pmu-events/arch/x86/arrowlake/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/arrowlake/pipeline.json @@ -1238,7 +1238,7 @@ "Counter": "0,1,2,3,4,5,6,7,8,9", "EventCode": "0xc0", "EventName": "INST_RETIRED.REP_ITERATION", - "PublicDescription": "Number of iterations of Repeat (REP) string = retired instructions such as MOVS, CMPS, and SCAS. Each has a byte, word, a= nd doubleword version and string instructions can be repeated using a repet= ition prefix, REP, that allows their architectural execution to be repeated= a number of times as specified by the RCX register. Note: Since the number= of iterations within a REP instruction can be significantly affected by fa= st strings, this event may vary run to run and not match the architectural = number of iterations (specified by RCX) Available PDIST counters: 0,1", + "PublicDescription": "Number of iterations of Repeat (REP) string = retired instructions such as MOVS, CMPS, and SCAS. Each has a byte, word, a= nd doubleword version and string instructions can be repeated using a repet= ition prefix, REP, that allows their architectural execution to be repeated= a number of times as specified by the RCX register. Note: Since the number= of iterations within a REP instruction can be significantly affected by fa= st strings, this event may vary from run to run and not match the architect= ural number of iterations (specified by RCX). Available PDIST counters: 0,1= ", "SampleAfterValue": "2000003", "UMask": "0x8", "Unit": "cpu_core" @@ -1931,7 +1931,7 @@ "Unit": "cpu_core" }, { - "BriefDescription": "Counts the number of LBR entries recorded. Re= quires LBRs to be enabled in IA32_LBR_CTL.", + "BriefDescription": "Counts the number of LBR entries recorded. Re= quires LBRs to be enabled in IA32_LBR_CTL. [This event is alias to LBR_INS= ERTS.ANY]", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xe4", "EventName": "MISC_RETIRED.LBR_INSERTS", @@ -1940,11 +1940,11 @@ "Unit": "cpu_atom" }, { - "BriefDescription": "LBR record is inserted", + "BriefDescription": "LBR record is inserted [This event is alias t= o LBR_INSERTS.ANY]", "Counter": "0,1,2,3,4,5,6,7,8,9", "EventCode": "0xe4", "EventName": "MISC_RETIRED.LBR_INSERTS", - "PublicDescription": "LBR record is inserted Available PDIST count= ers: 0,1", + "PublicDescription": "LBR record is inserted [This event is alias = to LBR_INSERTS.ANY] Available PDIST counters: 0,1", "SampleAfterValue": "1000003", "UMask": "0x1", "Unit": "cpu_core" diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-ev= ents/arch/x86/mapfile.csv index 748d1ee1605c..27eaf934b925 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -1,7 +1,7 @@ Family-model,Version,Filename,EventType GenuineIntel-6-(97|9A|B7|BA|BF),v1.41,alderlake,core GenuineIntel-6-BE,v1.41,alderlaken,core -GenuineIntel-6-C[56],v1.20,arrowlake,core +GenuineIntel-6-C[56],v1.21,arrowlake,core GenuineIntel-6-(1C|26|27|35|36),v5,bonnell,core GenuineIntel-6-(3D|47),v30,broadwell,core GenuineIntel-6-56,v12,broadwellde,core --=20 2.56.0.rc1.310.g51773c2048-goog