From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id B67C34A2064; Thu, 24 Sep 2026 15:28:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790263699; cv=none; b=MqTaIA+rqikV8yIlVSROtD0nNKMiwxIGPFoCgPd6Nayl0couz1hPZjkl092/GUDItij64v/NzO5xb7GoI/0s0MGv++94mpvLCxSk+zCYTknLWaKhhNkj1c19p87o7T8eJEGhX5Wfx1g+F54p/jI675cK3cUtwsjo6XK3iK42CCg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790263699; c=relaxed/simple; bh=mFas1w7I1cXL8LOHpUSEzdVwuRk8NVqBlgDk+CKwI4I=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=bKODbMAfKwGK5dMmRemoxmChxNv5dL13QQUmbv7eoLitT50RI3eshSRI7q35pgZn21pPV67To8+4D7McqH8IQRnqbSG2rzj4xCOTPAx6qSU049eJnz6hzk9oZwaNdjwS/OJ90V4+Jz2MyVwtrtag7x4j0RtVQR8Afn7Qe1+46No= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=Eqc6Q/eb; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="Eqc6Q/eb" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 672FA1A32; Thu, 24 Sep 2026 08:28:12 -0700 (PDT) Received: from e142021.arm.com (unknown [10.57.8.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 521473F86F; Thu, 24 Sep 2026 08:28:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1790263695; bh=mFas1w7I1cXL8LOHpUSEzdVwuRk8NVqBlgDk+CKwI4I=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Eqc6Q/ebhVfD9BuM1Na304lMAMpUhgGlhR65dJPXQdJMMmMRPQpIT6vt4n+dmY83e hK/ZkND9HV5dXwdt6FKXpKe8f1RrBI2R3V6NQEuE77EfeJvl88j/fNNLAQKfYjhbQ1 bguOKi5plKLLA28NhJqisqYEVCV7DSExMNI/JECI= From: Andre Przywara To: Lorenzo Pieralisi , Hanjun Guo , Sudeep Holla , Catalin Marinas , Will Deacon , "Rafael J . Wysocki" , Len Brown , James Morse , Ben Horgan , Reinette Chatre , Fenghua Yu Cc: Jonathan Cameron , Srivathsa L Rao , Ganapatrao Kulkarni , Trilok Soni , Srinivas Ramana , Niyas Sait , Lee Trager , Ritwick Sharma , Gavin Shan , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v11 03/13] arm_mpam: propagate MSC access errors for MBWU counters Date: Thu, 24 Sep 2026 17:27:29 +0200 Message-ID: <20260924152739.2865510-4-andre.przywara@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260924152739.2865510-1-andre.przywara@arm.com> References: <20260924152739.2865510-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Allow the mpam_msc_read_mbwu_l() function to return an error, and propagate errors from the lower level up. This also changes the users of this function. Signed-off-by: Andre Przywara Reviewed-by: Jonathan Cameron Reviewed-by: Ben Horgan Reviewed-by: Gavin Shan Tested-by: Gavin Shan # on NVIDIA Grace Hopper --- drivers/resctrl/mpam_devices.c | 45 +++++++++++++++++++++++----------- 1 file changed, 31 insertions(+), 14 deletions(-) diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c index 22069e7f7bb05..f780bcc587c7a 100644 --- a/drivers/resctrl/mpam_devices.c +++ b/drivers/resctrl/mpam_devices.c @@ -1132,8 +1132,9 @@ static bool mpam_ris_has_mbwu_long_counter(struct mpam_msc_ris *ris) mpam_has_feature(mpam_feat_msmon_mbwu_44counter, &ris->props)); } -static u64 mpam_msc_read_mbwu_l(struct mpam_msc *msc) +static int mpam_msc_read_mbwu_l(struct mpam_msc *msc, u64 *res) { + int ret; int retry = 3; u32 mbwu_l_low; u32 mbwu_l_high1, mbwu_l_high2; @@ -1143,20 +1144,30 @@ static u64 mpam_msc_read_mbwu_l(struct mpam_msc *msc) WARN_ON_ONCE((MSMON_MBWU_L + sizeof(u64)) > msc->mapped_hwpage_sz); WARN_ON_ONCE(!cpumask_test_cpu(smp_processor_id(), &msc->accessibility)); - __mpam_read_reg(msc, MSMON_MBWU_L + 4, &mbwu_l_high2); + ret = __mpam_read_reg(msc, MSMON_MBWU_L + 4, &mbwu_l_high2); + if (ret) + return ret; + do { mbwu_l_high1 = mbwu_l_high2; - __mpam_read_reg(msc, MSMON_MBWU_L, &mbwu_l_low); - __mpam_read_reg(msc, MSMON_MBWU_L + 4, &mbwu_l_high2); + ret = __mpam_read_reg(msc, MSMON_MBWU_L, &mbwu_l_low); + if (ret) + return ret; + ret = __mpam_read_reg(msc, MSMON_MBWU_L + 4, &mbwu_l_high2); + if (ret) + return ret; retry--; } while (mbwu_l_high1 != mbwu_l_high2 && retry > 0); - if (mbwu_l_high1 == mbwu_l_high2) - return ((u64)mbwu_l_high1 << 32) | mbwu_l_low; + if (mbwu_l_high1 == mbwu_l_high2) { + *res = ((u64)mbwu_l_high1 << 32) | mbwu_l_low; + } else { + pr_warn("Failed to read a stable value\n"); + *res = MSMON___L_NRDY; + } - pr_warn("Failed to read a stable value\n"); - return MSMON___L_NRDY; + return 0; } static void mpam_msc_zero_mbwu_l(struct mpam_msc *msc) @@ -1314,10 +1325,12 @@ static void __ris_msmon_read(void *arg) struct mpam_msc *msc = m->ris->vmsc->msc; u32 mon_sel, ctl_val, flt_val, cur_ctl, cur_flt; - if (!mpam_mon_sel_lock(msc)) { + ACQUIRE(mon_sel_lock, guard)(msc); + if (ACQUIRE_ERR(mon_sel_lock, &guard)) { m->err = -EIO; return; } + mon_sel = FIELD_PREP(MSMON_CFG_MON_SEL_MON_SEL, ctx->mon) | FIELD_PREP(MSMON_CFG_MON_SEL_RIS, ris->ris_idx); mpam_write_monsel_reg(msc, CFG_MON_SEL, mon_sel); @@ -1377,7 +1390,9 @@ static void __ris_msmon_read(void *arg) case mpam_feat_msmon_mbwu_44counter: case mpam_feat_msmon_mbwu_63counter: if (m->type != mpam_feat_msmon_mbwu_31counter) { - now = mpam_msc_read_mbwu_l(msc); + m->err = mpam_msc_read_mbwu_l(msc, &now); + if (m->err) + return; nrdy = now & MSMON___L_NRDY; if (m->type == mpam_feat_msmon_mbwu_63counter) @@ -1410,7 +1425,6 @@ static void __ris_msmon_read(void *arg) default: m->err = -EINVAL; } - mpam_mon_sel_unlock(msc); if (nrdy) m->err = -EBUSY; @@ -1771,6 +1785,7 @@ static int mpam_save_mbwu_state(void *arg) { int i; u64 val; + int ret; struct mon_cfg *cfg; u32 cur_flt, cur_ctl, mon_sel; struct mpam_msc_ris *ris = arg; @@ -1781,7 +1796,8 @@ static int mpam_save_mbwu_state(void *arg) mbwu_state = &ris->mbwu_state[i]; cfg = &mbwu_state->cfg; - if (WARN_ON_ONCE(!mpam_mon_sel_lock(msc))) + ACQUIRE(mon_sel_lock, guard)(msc); + if (ACQUIRE_ERR(mon_sel_lock, &guard)) return -EIO; mon_sel = FIELD_PREP(MSMON_CFG_MON_SEL_MON_SEL, i) | @@ -1792,7 +1808,9 @@ static int mpam_save_mbwu_state(void *arg) mpam_write_monsel_reg(msc, CFG_MBWU_CTL, 0); if (mpam_ris_has_mbwu_long_counter(ris)) { - val = mpam_msc_read_mbwu_l(msc); + ret = mpam_msc_read_mbwu_l(msc, &val); + if (ret) + return ret; mpam_msc_zero_mbwu_l(msc); } else { u32 val32; @@ -1808,7 +1826,6 @@ static int mpam_save_mbwu_state(void *arg) cfg->partid = FIELD_GET(MSMON_CFG_x_FLT_PARTID, cur_flt); mbwu_state->correction += val; mbwu_state->enabled = FIELD_GET(MSMON_CFG_x_CTL_EN, cur_ctl); - mpam_mon_sel_unlock(msc); } return 0; -- 2.43.0