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[199.106.103.254]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-145ac67c505sm1379403c88.5.2026.09.24.15.36.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Sep 2026 15:36:53 -0700 (PDT) Date: Thu, 24 Sep 2026 15:36:49 -0700 From: Jonathan Cameron To: Andre Przywara Cc: Lorenzo Pieralisi , Hanjun Guo , Sudeep Holla , Catalin Marinas , Will Deacon , "Rafael J . Wysocki" , Len Brown , James Morse , Ben Horgan , Reinette Chatre , Fenghua Yu , Jonathan Cameron , Srivathsa L Rao , Ganapatrao Kulkarni , Trilok Soni , Srinivas Ramana , Niyas Sait , Lee Trager , Ritwick Sharma , Gavin Shan , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v11 12/13] arm_mpam: change MPAM-Fb error IRQ to use a threaded IRQ handler Message-ID: <20260924153649.00001584@oss.qualcomm.com> In-Reply-To: <20260924152739.2865510-13-andre.przywara@arm.com> References: <20260924152739.2865510-1-andre.przywara@arm.com> <20260924152739.2865510-13-andre.przywara@arm.com> Organization: Qualcomm X-Mailer: Claws Mail 4.4.0 (GTK 3.24.51; x86_64-w64-mingw32) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=Wrq+otfv c=1 sm=1 tr=0 ts=6ab5a607 cx=c_pps a=cFYjgdjTJScbgFmBucgdfQ==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=kj9zAlcOel0A:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=7CQSdrXTAAAA:8 a=20KFwNOVAAAA:8 a=EUspDBNiAAAA:8 a=kM4gzuUOBcDNVL6HCnIA:9 a=CjuIK1q_8ugA:10 a=scEy_gLbYbu1JhEsrz4S:22 a=a-qgeE7W1pNrGK8U0ZQC:22 X-Proofpoint-ORIG-GUID: v9eYEJJfS9QWylIWeExKhUznFdJ4Ymn1 X-Proofpoint-GUID: v9eYEJJfS9QWylIWeExKhUznFdJ4Ymn1 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTI0MDA5MiBTYWx0ZWRfX1B+XOUahNwTW ZBqUZSl1TH4zCv0s8vcbJLxUlZGjwC1+D+/xzj/ycB8+czmQUB3wfRB0smwe6iPHVF/6ZjKGwOK 8MG15gVSXMJ+rl5cj9SfpVjg6eVgHf2fJVsjEIr/c/nvEDZCxCuI5s+DeVwK0DMQVu+3TDqSjrY 235maPbb0SpMRiKQzzQm5NADNXXPysips0Ngl92hx4mF9yldlACnMNS+LvmL9zBbVogPjEiqPHf TQuXZ/3tz9yHKFiR985Cq2wH3QQ1Nk/EoFEaESr2W5S9tc3a0Q71P9n6qZpOv/dLWjFN2o9ekCz V++kOq+imuP3e8Gmv1hXBcBhN3HJCrJZH+9BWDi8wpBLCQIcBQy73XyxXlyeRlvHeikmZB8SzLY 1OiPBorBKqhQrEdoAyedCxvrPFbf36oIzJM8zyfUQTq1+N0Zf55EP8bgA8E4zzyyjklHZLsAwOK l1QgiU5zThlsBjZUOBA== X-Proofpoint-Spam-Info: AW1haW4tMjYwOTI0MDA5MiBTYWx0ZWRfXwW02cr7Oz9tj 9E2bzDiJXXt78FyKnbpWGzuZrhnQAZS7riVyG+kNf5r9WpLMKQW7zy5uFqRwxM6bp5ojBCYAJew 4ED2LaoIqXj61yPObEWHQQ/Snkv5qaU= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-24_06,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 lowpriorityscore=0 adultscore=0 impostorscore=0 bulkscore=0 suspectscore=0 priorityscore=1501 clxscore=1015 malwarescore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609240092 On Thu, 24 Sep 2026 17:27:38 +0200 Andre Przywara wrote: > When an MPAM MSC gets into an error condition, it can trigger an error > IRQ. We cannot really do much about those errors, but we at least query > and log the error, then disable MPAM functionality. > > This error report relies on reading the MSC's error status register > (ESR) in the current hard-IRQ handler, which is not possible for MPAM-Fb > based MSC accesses, since they involve mailbox routines that might sleep. > The same is true for clearing the interrupt at the source, which requires > a (potentially sleeping) MSC access as well. > > Change the error IRQ handler to be a threaded interrupt, but keep the > handling in the hard-IRQ part for MMIO MSCs. This is needed since the > CPU affinity check in the MSC accessors requires a non-preemptible > context. > When the MSC is using an MPAM-Fb based access, we push the work into the > threaded part of the handler, where the accessors are allowed to sleep. > Also forbid per-CPU interrupts (PPIs) for MPAM-Fb, as we cannot use a > threaded IRQ here. > > The actual IRQ handler learns how to deal with errors. We cannot really > handle them, but we can try our best to disable the IRQ anyway. > Should the level IRQ line deactivation fail on the device side, we mask > the IRQ on the irqchip level, to prevent an interrupt storm. > > Signed-off-by: Andre Przywara > Reviewed-by: Gavin Shan > Reviewed-by: Srivathsa L Rao Reviewed-by: Jonathan Cameron