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AKwUvBw9w92s4+iOZdZ+O14sMuad6XTl2JD8P0VOSWc6mL5rc1mmPxHi4QY4XcEJ84xiyBIb0h8z31cc/i5UFT4=@vger.kernel.org X-Gm-Message-State: AFuF++kiq2v+sJB+y0p901uI7yUK/JPj+EaykVAiHwgkFlrXEdQ2511u piTmqR+/hQkdP60yWpPNV8D2aqJ7y1IJuzDbSj/Xyeaox1qBmATZAwReUius2GB8kfsZzz5xZOM 9tZw61mMAoA== X-Received: from dlbbt22.prod.google.com ([2002:a05:7022:996:b0:143:8c20:9c79]) (user=irogers job=prod-delivery.src-stubby-dispatcher) by 2002:a05:701b:4515:10b0:145:156:8e72 with SMTP id a92af1059eb24-14504007746mr2570153c88.26.1790269442209; Thu, 24 Sep 2026 10:04:02 -0700 (PDT) Date: Thu, 24 Sep 2026 10:03:22 -0700 In-Reply-To: <20260924170346.3872848-1-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260924053645.3555041-1-irogers@google.com> <20260924170346.3872848-1-irogers@google.com> X-Mailer: git-send-email 2.56.0.rc1.315.gc6ed9934b7-goog Message-ID: <20260924170346.3872848-3-irogers@google.com> Subject: [PATCH v2 02/26] perf vendor events intel: Update alderlaken events from 1.40 to 1.41 From: Ian Rogers To: irogers@google.com, acme@kernel.org, dapeng1.mi@linux.intel.com, namhyung@kernel.org, edward.baker@intel.com, perry.taylor@intel.com, eranian@google.com Cc: adrian.hunter@intel.com, afaerber@suse.de, ctshao@google.com, james.clark@linaro.org, jolsa@kernel.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, mani@kernel.org, mingo@redhat.com, peterz@infradead.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable The updated events were published in: https://github.com/intel/perfmon/commit/5d7b37d5671a49c72abf735dc81d147c7= 776119c Signed-off-by: Ian Rogers --- tools/perf/pmu-events/arch/x86/alderlaken/cache.json | 4 ++-- tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/alderlaken/cache.json b/tools/p= erf/pmu-events/arch/x86/alderlaken/cache.json index b39c73614b86..38851c1580c1 100644 --- a/tools/perf/pmu-events/arch/x86/alderlaken/cache.json +++ b/tools/perf/pmu-events/arch/x86/alderlaken/cache.json @@ -4,7 +4,7 @@ "Counter": "0,1,2,3,4,5", "EventCode": "0x31", "EventName": "CORE_REJECT_L2Q.ANY", - "PublicDescription": "Counts the number of (demand and L1 prefetch= ers) core requests rejected by the L2 queue (L2Q) due to a full or nearly f= ull condition, which likely indicates back pressure from L2Q. It also coun= ts requests that would have gone directly to the External Queue (XQ), but a= re rejected due to a full or nearly full condition, indicating back pressur= e from the IDI link. The L2Q may also reject transactions from a core to = ensure fairness between cores, or to delay a cores dirty eviction when the = address conflicts incoming external snoops. (Note that L2 prefetcher reque= sts that are dropped are not counted by this event). Counts on a per core = basis.", + "PublicDescription": "Counts the number of core requests (demand a= nd L1 prefetchers) rejected by the L2 queue (L2Q) due to a full or nearly f= ull condition, which likely indicates back pressure from L2Q. It also count= s requests that would have gone directly to the External Queue (XQ) but are= rejected due to a full or nearly full condition, indicating back pressure = from the IDI link. The L2Q may also reject transactions from a core to ensu= re fairness between cores, or to delay a cores dirty eviction when the addr= ess conflicts with incoming external snoops. (Note that L2 prefetcher reque= sts that are dropped are not counted by this event). Counts on a per core b= asis.", "SampleAfterValue": "200003" }, { @@ -12,7 +12,7 @@ "Counter": "0,1,2,3,4,5", "EventCode": "0x30", "EventName": "L2_REJECT_XQ.ANY", - "PublicDescription": "Counts the number of demand and prefetch tra= nsactions that the External Queue (XQ) rejects due to a full or near full c= ondition which likely indicates back pressure from the IDI link. The XQ ma= y reject transactions from the L2Q (non-cacheable requests), BBL (L2 misses= ) and WOB (L2 write-back victims).", + "PublicDescription": "Counts the number of demand and prefetch tra= nsactions that the External Queue (XQ) rejects due to a full or near full c= ondition, which likely indicates back pressure from the IDI link. The XQ ma= y reject transactions from the L2Q (non-cacheable requests), BBL (L2 misses= ) and WOB (L2 write-back victims).", "SampleAfterValue": "200003" }, { diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-ev= ents/arch/x86/mapfile.csv index 866b5fba7124..748d1ee1605c 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -1,6 +1,6 @@ Family-model,Version,Filename,EventType GenuineIntel-6-(97|9A|B7|BA|BF),v1.41,alderlake,core -GenuineIntel-6-BE,v1.40,alderlaken,core +GenuineIntel-6-BE,v1.41,alderlaken,core GenuineIntel-6-C[56],v1.20,arrowlake,core GenuineIntel-6-(1C|26|27|35|36),v5,bonnell,core GenuineIntel-6-(3D|47),v30,broadwell,core --=20 2.56.0.rc1.315.gc6ed9934b7-goog