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Thu, 24 Sep 2026 12:06:19 -0700 Received: from inno-dell.home (10.127.8.10) by mail.nvidia.com (10.129.68.10) with Microsoft SMTP Server id 15.2.2562.49 via Frontend Transport; Thu, 24 Sep 2026 12:06:10 -0700 From: Zhi Wang To: , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , Peter Colberg , Zhi Wang Subject: [PATCH v2 1/8] rust: pci: add {enable,disable}_sriov(), to control SR-IOV capability Date: Thu, 24 Sep 2026 22:05:48 +0300 Message-ID: <20260924190556.1620886-2-zhiw@nvidia.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260924190556.1620886-1-zhiw@nvidia.com> References: <20260924190556.1620886-1-zhiw@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000044A3:EE_|IA1PR12MB7543:EE_ X-MS-Office365-Filtering-Correlation-Id: e9f7ea27-fa76-4e45-5b8d-08df1a6eff84 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|23010399003|376014|7416014|36860700016|3023799007|10067099003|11063799006|56012099006|6133799003|18002099003|22082099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: TO22sgmPzTbICIdUhb+K+14mjoAYID6yJ564v2yfOl+ucNgRopGF9XqnYLOacIfNuL7TKfjlsZeCYfRhwfAG0oO6xX3J368+/pCeQlt6/yijn6kfEg4viYnQdiMHFJNWdCnbyXsphGUGwpGleKNunKRgtMWLrKOmKKWBOQZOjIscmV5zIt2ItZ6quA31V+ku61GtfewdGCnIaIgHwUOOSXQJs1RqHbxHccdn1cc6Gkm/7DSMImk0dYDjwfLhqCMKEKJe+qXmEp0u2AT/R0ejuijHI6GKf4y6WJP6RVf8o3Cgo1apYwHdviouMixGWHlnAc0blVhbJxdCHZkcb9foxKXHCANNijuPfW8pgWDLUCkFfg1noCismHKDqKeed0A+OMeVxgjG/yfqXCnBw50YdsII/OOvlkqTUsi8X5AkNDK1ZArrXA737oE2rXyHemSg X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Sep 2026 19:06:54.3675 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e9f7ea27-fa76-4e45-5b8d-08df1a6eff84 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044A3.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB7543 From: Peter Colberg Add methods to enable and disable the Single Root I/O Virtualization (SR-IOV) capability for a PCI device. The wrapped C methods take care of validating whether the device is a Physical Function (PF), whether SR-IOV is currently disabled (or enabled), and whether the number of requested VFs does not exceed the total number of supported VFs. Synchronously disable SR-IOV in the Rust PCI remove callback before unbinding the PF driver. This ensures that when a Virtual Function (VF) is bound to a driver, the corresponding Physical Function (PF) is bound to a driver, too, which is a prerequisite for exposing a safe Rust API that allows a VF driver to obtain the PF device for a VF device and subsequently access the private data of the PF driver. Suggested-by: Danilo Krummrich Signed-off-by: Peter Colberg Signed-off-by: Zhi Wang --- rust/kernel/pci.rs | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/rust/kernel/pci.rs b/rust/kernel/pci.rs index 3ec897709e89..e6dac919f02d 100644 --- a/rust/kernel/pci.rs +++ b/rust/kernel/pci.rs @@ -133,6 +133,10 @@ extern "C" fn remove_callback(pdev: *mut bindings::pci_dev) { // INVARIANT: `pdev` is valid for the duration of `remove_callback()`. let pdev = unsafe { &*pdev.cast::>>() }; + // Keep PF data installed until all VF remove callbacks have completed. + #[cfg(CONFIG_PCI_IOV)] + pdev.disable_sriov(); + // SAFETY: `remove_callback` is only ever called after a successful call to // `probe_callback`, hence it's guaranteed that `Device::set_drvdata()` has been called // and stored a `Pin>>`. @@ -472,6 +476,38 @@ pub fn set_master(&self) { // SAFETY: `self.as_raw` is guaranteed to be a pointer to a valid `struct pci_dev`. unsafe { bindings::pci_set_master(self.as_raw()) }; } + + /// Enable the Single Root I/O Virtualization (SR-IOV) capability for this device, + /// where `nr_virtfn` is number of Virtual Functions (VF) to enable. + #[cfg(CONFIG_PCI_IOV)] + pub fn enable_sriov(&self, nr_virtfn: i32) -> Result { + // SAFETY: + // `self.as_raw` returns a valid pointer to a `struct pci_dev`. + // + // `pci_enable_sriov()` checks that the enable operation is valid: + // - the device is a Physical Function (PF), + // - SR-IOV is currently disabled, and + // - `nr_virtfn` does not exceed the total number of supported VFs. + // + // The Core device context inherits from the Bound device context, + // which guarantees that the PF device is bound to a driver. + to_result(unsafe { bindings::pci_enable_sriov(self.as_raw(), nr_virtfn) }) + } + + /// Disable the Single Root I/O Virtualization (SR-IOV) capability for this device. + #[cfg(CONFIG_PCI_IOV)] + pub fn disable_sriov(&self) { + // SAFETY: + // `self.as_raw` returns a valid pointer to a `struct pci_dev`. + // + // `pci_disable_sriov()` checks that the disable operation is valid: + // - the device is a Physical Function (PF), and + // - SR-IOV is currently enabled. + // + // The Core device context inherits from the Bound device context, + // which guarantees that the PF device is bound to a driver. + unsafe { bindings::pci_disable_sriov(self.as_raw()) }; + } } // SAFETY: `pci::Device` is a transparent wrapper of `struct pci_dev`. -- 2.53.0