Re: [RFC PATCH net-next v3 4/5] net: dsa: qca8k: flag QCA8337 internal CPU PHYs for SmartSpeed

[Yongzhao Chen <yongzhao.derek@gmail.com>]

Hi Andrew,

The register 0x14 configuration is in patch 5. For a QCA8337 CPU PHY
marked by patch 4, qca8337_soft_reset() clears SmartSpeed enable and
bypass before the software reset. I should have made that relationship
explicit in patch 4.

I have a local read_status change for QCA8337, which I plan to include
in the next RFC. When autonegotiation is enabled, it reads the resolved
speed and duplex from register 0x11, retaining generic link-partner and
master/slave handling. It holds the link down until those values are
valid; forced mode keeps the generic BMCR handling. Local tests that run
the callback and the PHY state machine against a simulated MDIO bus
pass, including a case where 0x11 reports 100 Mb/s while the generic
path resolves 1 Gb/s. W=1 object builds for x86 and arm64 are clean.

I also tested it on RA74 in an OpenWrt backport on Linux 6.18.52, not
the net-next series itself, with the existing CPU SmartSpeed workaround.
On normal 100 and 1000 Mb/s LAN links the reported speed matched 0x11,
including after renegotiating the 100 Mb/s port and after a warm
reboot. These were normal links; I could not force a downshift, so the
downshifted case is only covered by the simulated test.

The existing at803x downshift tunable cannot be reused directly here.
Its setter calls phy_init_hw() after writing 0x14, which would run
qca8337_soft_reset() and clear a requested enable on the flagged CPU
PHY. This shared-port PHY also has no net_device->phydev through which
ethtool can reach it; ethtool on the conduit or wan addresses a
different PHY. I have left tunable support out of this follow-up.

I don't know whether downshift is broken in general or only in
switch-integrated PHYs. My only data point is the RA74 CPU link
failure, and I have no downshift results from user ports or discrete
at803x PHYs. phydev->is_internal is set for every PHY that qca83xx
matches, since they are all switch-internal, including user ports and
QCA8327, so it cannot select just the CPU link. I have not found a
verified erratum for this switch revision.

Thanks,
Yongzhao Chen