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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by SJ1PEPF000023D2.mail.protection.outlook.com (10.167.244.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.451.8 via Frontend Transport; Fri, 25 Sep 2026 11:43:12 +0000 Received: from purico-abeahost.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.49; Fri, 25 Sep 2026 06:43:06 -0500 From: Shivansh Dhiman To: , , , CC: , , , , , , , , , , , , , Subject: [PATCH v3 2/9] KVM: SVM: Disable interception of FRED MSRs for FRED supported guests Date: Fri, 25 Sep 2026 11:40:10 +0000 Message-ID: <20260925114017.2208531-3-shivansh.dhiman@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260925114017.2208531-1-shivansh.dhiman@amd.com> References: <20260925114017.2208531-1-shivansh.dhiman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000023D2:EE_|IA0PR12MB8253:EE_ X-MS-Office365-Filtering-Correlation-Id: 5f47357f-87aa-4178-02f9-08df1afa2dde X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|1800799024|82310400026|23010399003|36860700016|10067099003|56012099006|11063799006|22082099003|18002099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 2OJCzggrnFFUG/h+v5+gVaj6Z7gD1YDb3azrnyHfOn3mxpe74OhrjYcQVdzIJYZKZW8klJeW7WpaP5dGEmdP9TQMR05QN+Pza//3ISk7gDIFIcYIT8UVgoVIuc+MJ/RvOKLvJMhr/kOZBVhCMeIohg1uU7/EMARqwNBIdHqWcB1h6aq/p3koMpWooiBBIi6U2HL6cHzJysy0uPK7guK+QxakiJbNzfqMfTBTxT3L/gFTipcRpWZ0Jxm97i6ocf0jp0fwVqXhGK30/fYZxUH9vwASv1KAzbyS7bzlqIbp/tiWaDMUFEqAWoDjfkFjJp+e7kYGLNuEY5AFi54Ih9qy8y5vwZNrqRHJyYOLO0Sleb7aqmvwuTpYJ6jU8s8XBsIyRmR06gCsbD+ILOzHoq7GsvbpSeYMjJYzUg7SdRRJcPqA0WlkGx1QKLev/kgq7P51 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Sep 2026 11:43:12.2296 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5f47357f-87aa-4178-02f9-08df1afa2dde X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023D2.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8253 The FRED (Flexible Return and Event Delivery) feature introduces a new set of MSRs for managing its state, such as MSR_IA32_FRED_CONFIG and the various stack pointer MSRs. For a guest that has FRED enabled via its CPUID bits, the guest OS expects to be able to directly read and write these MSRs. Intercepting these accesses would cause unnecessary VM-Exits and performance overhead. In addition, the state of the MSRs at any point should always correspond to the context (host or guest) which is running. Otherwise, the event delivery could refer to wrong MSR values. Co-developed-by: Neeraj Upadhyay Signed-off-by: Neeraj Upadhyay Signed-off-by: Shivansh Dhiman --- Changes in v3: * Rebased, no functional changes. Changes in v2: * Used guest_cpu_cap_has() instead of checking VMCB bit (Sean Christopherson). * Variable rename from 'fred_enable' to 'intercept' (Sean Christopherson). --- arch/x86/kvm/svm/svm.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index 6d55b0a576d9..e212f53d262a 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -788,6 +788,21 @@ static void svm_recalc_pmu_msr_intercepts(struct kvm_vcpu *vcpu) MSR_TYPE_RW, intercept); } +static void svm_recalc_fred_msr_intercepts(struct kvm_vcpu *vcpu) +{ + bool intercept = guest_cpu_cap_has(vcpu, X86_FEATURE_FRED); + + svm_set_intercept_for_msr(vcpu, MSR_IA32_FRED_RSP0, MSR_TYPE_RW, !intercept); + svm_set_intercept_for_msr(vcpu, MSR_IA32_FRED_RSP1, MSR_TYPE_RW, !intercept); + svm_set_intercept_for_msr(vcpu, MSR_IA32_FRED_RSP2, MSR_TYPE_RW, !intercept); + svm_set_intercept_for_msr(vcpu, MSR_IA32_FRED_RSP3, MSR_TYPE_RW, !intercept); + svm_set_intercept_for_msr(vcpu, MSR_IA32_FRED_STKLVLS, MSR_TYPE_RW, !intercept); + svm_set_intercept_for_msr(vcpu, MSR_IA32_FRED_SSP1, MSR_TYPE_RW, !intercept); + svm_set_intercept_for_msr(vcpu, MSR_IA32_FRED_SSP2, MSR_TYPE_RW, !intercept); + svm_set_intercept_for_msr(vcpu, MSR_IA32_FRED_SSP3, MSR_TYPE_RW, !intercept); + svm_set_intercept_for_msr(vcpu, MSR_IA32_FRED_CONFIG, MSR_TYPE_RW, !intercept); +} + static void svm_recalc_msr_intercepts(struct kvm_vcpu *vcpu) { struct vcpu_svm *svm = to_svm(vcpu); @@ -857,6 +872,7 @@ static void svm_recalc_msr_intercepts(struct kvm_vcpu *vcpu) sev_es_recalc_msr_intercepts(vcpu); svm_recalc_pmu_msr_intercepts(vcpu); + svm_recalc_fred_msr_intercepts(vcpu); /* * x2APIC intercepts are modified on-demand and cannot be filtered by -- 2.43.0