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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by BN7PEPF000000A3.mail.protection.outlook.com (10.167.248.155) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.451.8 via Frontend Transport; Fri, 25 Sep 2026 11:44:31 +0000 Received: from purico-abeahost.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.49; Fri, 25 Sep 2026 06:44:26 -0500 From: Shivansh Dhiman To: , , , CC: , , , , , , , , , , , , , Subject: [PATCH v3 6/9] KVM: SVM: Support FRED nested exception injection Date: Fri, 25 Sep 2026 11:40:14 +0000 Message-ID: <20260925114017.2208531-7-shivansh.dhiman@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260925114017.2208531-1-shivansh.dhiman@amd.com> References: <20260925114017.2208531-1-shivansh.dhiman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN7PEPF000000A3:EE_|DS7PR12MB6239:EE_ X-MS-Office365-Filtering-Correlation-Id: 27ff011c-576d-474f-91a4-08df1afa5d38 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|1800799024|82310400026|23010399003|36860700016|3023799007|10067099003|56012099006|11063799006|22082099003|18002099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: y1bzpo05RsPOIBCz4ElIUhot4M9/JvFl2f7y2EXfeXFkPt6KPSqCWpcbklH48ncfWWvCnR55FStIa6xIJyfACFJsdTj3TIyWU6jgOWK7yGMJnJfw+1V1bgWr77LBvjcTYeOVr8NW/358dfbbn2tQH3io/rDQPBpNYJctbIVGNmUBU8EtwpuRHYuqy9DgwnER/Lx0zDB7MtapGqiPBLCviNadbIX79irSmvMTR5L4hGNyNJuJK8A6kh6J9j/ZmqjC8iGtLNONvCbPZTR0tyfs/1pWEQunUVbDOE1s9A4wxKCDqMjN5rObp8awf2BlguJYsrcV9ctuE/f7mbRm2QELSnDQPRAvOOT6s5WyWHUGbLsv3Yz8F4C4hX/DYRo96rBTV3wuycrmbZ0aUQwxfLgax00N4uxi2LUVR8oUCXd0iLbHlQMBVJ+WfTB4Iw9Tm2ea X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Sep 2026 11:44:31.7587 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 27ff011c-576d-474f-91a4-08df1afa5d38 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN7PEPF000000A3.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6239 From: Neeraj Upadhyay Set the SVM nested exception bit in EVENT_INJECTION_CTL when injecting a nested exception using FRED event delivery to ensure: 1) A nested exception is injected on a correct stack level. 2) The nested bit defined in FRED stack frame is set. The event stack level used by FRED event delivery depends on whether the event was a nested exception encountered during delivery of an earlier event, because a nested exception is "regarded" as happening on ring 0. E.g., when #PF is configured to use stack level 1 in IA32_FRED_STKLVLS MSR: - nested #PF will be delivered on the stack pointed by FRED_RSP1 MSR when encountered in ring 3 and ring 0. - normal #PF will be delivered on the stack pointed by FRED_RSP0 MSR when encountered in ring 3. The SVM nested-exception support ensures a correct event stack level is chosen when a VM entry injects a nested exception. Signed-off-by: Neeraj Upadhyay Co-developed-by: Shivansh Dhiman Signed-off-by: Shivansh Dhiman Reviewed-by: Nikunj A Dadhania --- Changes in v3: * Use ex->is_nested to check for nested exceptions. Changes in v2: * Replace variable 'nested' with 'is_nested' (Sean Christopherson). * Formatted variables in reverse fir-tree order (Sean Christopherson). --- arch/x86/include/asm/svm.h | 1 + arch/x86/kvm/svm/svm.c | 5 ++++- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/svm.h b/arch/x86/include/asm/svm.h index 0570581e251a..1a6d4509b05b 100644 --- a/arch/x86/include/asm/svm.h +++ b/arch/x86/include/asm/svm.h @@ -664,6 +664,7 @@ static inline void __unused_size_checks(void) #define SVM_EVTINJ_VALID (1 << 31) #define SVM_EVTINJ_VALID_ERR (1 << 11) +#define SVM_EVTINJ_NESTED_EXCEPTION (1 << 13) #define SVM_EVTINJ_RESERVED_BITS ~(SVM_EVTINJ_VEC_MASK | SVM_EVTINJ_TYPE_MASK | \ SVM_EVTINJ_VALID_ERR | SVM_EVTINJ_VALID) diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index 6c15e8480d25..fb6b94405f88 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -389,6 +389,7 @@ static int svm_update_soft_interrupt_rip(struct kvm_vcpu *vcpu, u8 vector) static void svm_inject_exception(struct kvm_vcpu *vcpu) { struct kvm_queued_exception *ex = &vcpu->arch.exception; + bool is_nested = is_fred_enabled(vcpu) && ex->is_nested; struct vcpu_svm *svm = to_svm(vcpu); kvm_deliver_exception_payload(vcpu, ex); @@ -400,6 +401,7 @@ static void svm_inject_exception(struct kvm_vcpu *vcpu) svm->vmcb->control.event_inj = ex->vector | SVM_EVTINJ_VALID | (ex->has_error_code ? SVM_EVTINJ_VALID_ERR : 0) + | (is_nested ? SVM_EVTINJ_NESTED_EXCEPTION : 0) | SVM_EVTINJ_TYPE_EXEPT; if (is_fred_enabled(vcpu)) @@ -4502,7 +4504,8 @@ static void svm_complete_interrupts(struct kvm_vcpu *vcpu) kvm_requeue_exception(vcpu, vector, exitintinfo & SVM_EXITINTINFO_VALID_ERR, - error_code, false, event_data); + error_code, exitintinfo & SVM_EVTINJ_NESTED_EXCEPTION, + event_data); break; } case SVM_EXITINTINFO_TYPE_INTR: -- 2.43.0