From: Ard Biesheuvel <ardb+git@google.com>
To: 0001-PCI-Tolerate-non-prefetchable-64-bit-BARs-in-prefetc.patch@google.com
Cc: linux-kernel@vger.kernel.org, "Ard Biesheuvel" <ardb@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>
Subject: [PATCH v2 0/2] PCI: Allow non-prefetchable BARs in prefetchable windows
Date: Fri, 25 Sep 2026 18:47:53 +0200 [thread overview]
Message-ID: <20260925164801.4047844-4-ardb+git@google.com> (raw)
From: Ard Biesheuvel <ardb@kernel.org>
The non-prefetchable window of a PCI-to-PCI bridge can only decode
32-bit addresses, and so even 64-bit non-prefetchable BARs of devices
below a bridge compete for the scarce MMIO space below 4 GB.
The PCIe spec notes that marking such a BAR prefetchable still permits
correct operation as long as the entire path from the host to the device
is PCIe (PCIe r7.0, sec 7.5.1.2.1). The same applies when the OS places
a non-prefetchable BAR in a prefetchable bridge window, and so this
series permits that unless there is a bridge on the path to the root bus
that is not a PCIe Root Port or Switch Port, allowing 64-bit
non-prefetchable BARs to be placed above 4 GB.
How a host bridge treats the windows that firmware describes as
prefetchable is platform specific, however, and so this is only done if
the host bridge has no prefetchable windows at all, in which case all
prefetchable bridge windows are carved out of non-prefetchable host
bridge windows. This also means that devices on a root bus are never
affected.
Patch #1 is a preparatory refactor of pci_bus_alloc_resource() with no
functional change, and patch #2 implements the relaxation.
The series is based on pci/for-linus, as patch #2 touches the same
lines in pci_do_resource_release_and_resize() as commit d58384c22739
("PCI: Fix BAR resize for devices on a root bus") queued there for
v7.3.
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>
Cc: Lorenzo Pieralisi <lpieralisi@kernel.org>
Link: https://lore.kernel.org/linux-pci/20260910143440.3865663-2-ardb+git@google.com/
Ard Biesheuvel (2):
PCI: Add __pci_bus_alloc_resource() to allocate with explicit flags
PCI: Allow non-prefetchable BARs in prefetchable windows
drivers/pci/bus.c | 70 ++++++++++++++++--------
drivers/pci/pci.c | 115 +++++++++++++++++++++++++++++++++++++++-
drivers/pci/pci.h | 11 +++-
drivers/pci/setup-bus.c | 58 +++++++++++++-------
drivers/pci/setup-res.c | 29 ++++++----
5 files changed, 228 insertions(+), 55 deletions(-)
base-commit: 9a8daf68b9b30c536b0991d9f098ed0db80abc1c
--
2.56.0.rc1.315.gc6ed9934b7-goog
next reply other threads:[~2026-09-25 16:48 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-25 16:47 Ard Biesheuvel [this message]
2026-09-25 16:47 ` [PATCH v2 1/2] PCI: Add __pci_bus_alloc_resource() to allocate with explicit flags Ard Biesheuvel
2026-09-25 16:47 ` [PATCH v2 2/2] PCI: Allow non-prefetchable BARs in prefetchable windows Ard Biesheuvel
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