From: Vishal Badole <Vishal.Badole@amd.com>
To: <bp@alien8.de>, <yazen.ghannam@amd.com>, <tony.luck@intel.com>,
<linux-edac@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Cc: Vishal Badole <Vishal.Badole@amd.com>
Subject: [PATCH 0/2] EDAC/amd64: Consolidate Family 1Ah setup and fix UMC csrow decode
Date: Fri, 25 Sep 2026 22:56:37 +0530 [thread overview]
Message-ID: <20260925172639.97063-1-Vishal.Badole@amd.com> (raw)
Two small amd64_edac cleanups/fixes for AMD Family 1Ah.
Patch 1 sets zn_regs_v2 once at the Family 1Ah level instead of in each
model case, so future models cannot miss the v2 register layout. No
functional change.
Patch 2 masks the UMC chip select from MCA_SYND with 0x3 instead of 0x7.
Only four chip selects are ever implemented, so the old mask could decode
an out-of-range csrow and trip an EDAC core warning.
Vishal Badole (2):
EDAC/amd64: Set zn_regs_v2 for all Family 1Ah models
EDAC/amd64: Mask UMC chip select to the four implemented selects
drivers/edac/amd64_edac.c | 10 +++-------
1 file changed, 3 insertions(+), 7 deletions(-)
--
2.34.1
next reply other threads:[~2026-09-25 17:27 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-25 17:26 Vishal Badole [this message]
2026-09-25 17:26 ` [PATCH 1/2] EDAC/amd64: Set zn_regs_v2 for all Family 1Ah models Vishal Badole
2026-09-25 17:26 ` [PATCH 2/2] EDAC/amd64: Mask UMC chip select to the four implemented selects Vishal Badole
2026-09-25 18:14 ` Borislav Petkov
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